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publication# 10216 rev. f amendment /0 issue date: june 1993 advanced micro devices am85c30 enhanced serial communications controller final distinctive characteristics n fastest data rate of any am8530 8.192 mhz / 2.048 mb/s 10 mhz / 2.5 mb/s 16.384 mhz / 4.096 mb/s n low-power cmos technology n pin and function compatible with other nmos and cmos 8530s n easily interfaced with most cpus compatible with non-multiplexed bus n many enhancements over nmos am8530h allows am85c30 to be used more effectively in high-speed applications improves interface capabilities n two independent full-duplex serial channels n asynchronous mode features programmable stop bits, clock factor, character length and parity break detection/generation error detection for framing, overrun, and parity n synchronous mode features supports ibm a bisync, sdlc, sdlc loop, hdlc, and adccp protocols programmable crc generators and checkers sdlc/hdlc support includes frame control, zero insertion and deletion, abort, and residue handling n enhanced scc functions support high-speed frame reception using dma 14-bit byte counter 10 19 sdlc/hdlc frame status fifo independent control on both channels enhanced operation does not allow special receive conditions to lock the 3-byte data fifo when the 10 19 fifo is enabled n local loopback and auto echo modes n internal or external character synchronization n 2-mb/s fm encoding transmit and receive capability using internal dpll for 16.384-mhz product n internal synchronization between rxc to pclk and txc to pclk this allows the user to eliminate external syn- chronization hardware required by the nmos device when transmitting or receiving data at the maximum rate of 1/4 pclk frequency general description amds am85c30 is an enhanced pin-compatible ver- sion of the popular am8530h serial communications controller. the enhanced serial communications controller (escc) is a high-speed, low-power, multi- protocol communications peripheral designed for use with 8- and 16-bit microprocessors. it has two independ- ent,full-duplex channels and functions as a serial-to- parallel, parallel-to-serial converter/controller. amds proprietary enhancements make the am85c30 easier to interface and more effective in high-speed applica- tions due to a reduction in software burden and the elimi- nation of the need for some external glue logic. the am85c30 is easy to use due to a variety of sophisti- cated internal functions, including on-chip baud rate generators, digital phase-locked loops, and crystal oscillators, which dramatically reduce the need for ex- ternal logic. the device can generate and check crc codes in any sync mode, and can be programmed to check data integrity in various modes. the escc also has facilities for modem controls in both channels. in ap- plications where these controls are not needed, the mo- dem controls can be used for general-purpose i/o. this versatile device supports virtually any serial data transfer application such as networks, modems, cas- settes, and tape drivers. the escc is designed for non- multiplexed buses and is easily interfaced with most cpus, such as 80188, 80186, 80286, 8080, z80, 6800, 68000 and multibus ? .
amd 2 am85c30 enhancements that allow the am85c30 to be used more effectively in high-speed applications include: n a 10 19 bit sdlc/hdlc frame status fifo array n a 14-bit sdlc/hdlc frame byte counter n automatic sdlc/hdlc opening frame flag transmission n txd pin forced high in sdlc nrzi mode after closing flag n automatic sdlc/hdlc tx underrun/eom flag reset n automatic sdlc/hdlc tx crc generator reset/ preset n rts synchronization to closing sdlc/hdlc flag dtr / req deactivation delay significantly reduced n external pclk to rxc or txc synchronization requirement eliminated for pclk divide-by-four operation other enhancements to improve the am85c30 inter- face capabilities include: n write data valid setup time to falling edge of wr requirement eliminated n reduced int response time n reduced access recovery time (t rc ) to 3 pclk best case (3 1/2 pclk worst case) n improved wait timing n write registers wr3, wr4, wr5, and wr10 made readable n lower priority interrupt masking without intack n complete sdlc/hdlc crc character reception block diagram data control cpu bus vo internal control logic internal bus channel a registers interrupt control logic channel b registers +5 v gnd pclk channel a channel b control logic transmitter receiver baud rate generator 10 19 bit frame status fifo interrupt control lines 5 10216f-1 8 txda rxda rtxca trxca dtr/reqa synca w/reqa rtsa ctsa dcda txdb rxdb rtxcb trxcb dtr/reqb syncb w/reqb rtsb ctsb dcdb related amd products part no. description part no. description am7960 coded data transceiver am9517a dma controller 80186 highly integrated 16-bit 5380, 53c80 scsi bus controller microprocessor 80188 highly integrated 8-bit 80286, 80c286 high-performance 16-bit microprocessor microprocessor am386 high-performance 32-bit microprocessor
amd 3 am85c30 connection diagrams top view d 0 d 2 d 4 d 6 rd wr a/ b 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 am85c30 10216f-2 10216f-3 note: pin 1 is marked for orientation. dip d 1 d 3 d 5 d 7 int ieo iei intack +5 v w/reqa synca rtxca rxda trxca txda dtr/reqa rtsa ctsa dcda pclk ce d/ c gnd w/reqb syncb rtxcb rxdb trxcb txdb dtr/reqb rtsb ctsb dcdb 1 44 43 42 5 4 3 2 641 40 7 8 9 10 11 12 13 14 15 16 17 23 24 25 26 19 20 21 22 18 27 28 39 38 37 36 35 34 33 32 31 30 29 ieo iei intack +5 v w / reqa synca rtxca rxda trxca txda nc a/ b ce d/ c nc gnd w / reqb syncb rtxcb rxdb trxcb txdb int d 7 d 5 d 3 d 1 d 0 d 2 d 4 d 6 rd wr nc dtr / reqa rtsa ctsa dcda pclk dcdb ctsb rtsb dtr / reqb nc plcc, lcc logic symbol d 7 Cd 0 rd wr a/ b ce d/ c txda rxda trxca rtxca synca w / reqa dtr / reqa rtsa ctsa dcda txdb rxdb trxcb rtxcb serial data channel clocks channel controls for modem, dma, or other serial data channel clocks data bus control +5 v gnd pclk 8 channel controls for modem, dma, or other bus timing and reset interrupt 10216f-4 syncb w/reqb dtr/reqb rtsb ctsb dcdb int intack iei ie0
amd 4 am85c30 ordering information commodity products -8 = 8.192 mhz -10 = 10 mhz -16 = 16.384 mhz amd commodity products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of: am85c30 p c optional processing temperature range c = commercial (0 to +70 c) package type p = 40-pin plastic dip (pd 040) j = 44-pin plastic leaded chip carrier (pl 044) speed option device number/description am85c30 enhanced serial communications controller blank = standard processing valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and check on newly released combinations. valid combinations am85c30-8 am85c30-10 am85c30-16 pc, jc -10
amd 5 am85c30 ordering information industrial products amd industrial products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of: am85c30 j i i = industrial (-40 to +85 c) j = 44-pin leadless chip carrier (pl 044) -10 = 10 mhz -16 = 16.384 mhz am85c30 enhanced serial communications controller blank = standard processing valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and check on newly released combinations. valid combinations am85c30-10 am85c30-16 ji -10 optional processing temperature range package type speed option device number/description
amd 6 am85c30 military ordering information apl products amd products for aerospace and defense applications are available in several packages and operating ranges. apl (approved products list) products are fully compliant with mil-std-883 requirements. the order number (valid combination) is formed by a combination of: am85c30 b u lead finish package type u = 44-pin leadless chip carrier (cl 044) q = 40-pin ceramic dip (cd 040) device class /b = class b speed option -8 = 8.192 mhz -10 = 10 mhz -16 = 16.384 mhz device number/description am85c30 enhanced serial communications controller valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and check on newly released combinations. valid combinations bqa, bua a a = hot solder dip -10 am85c30-8 am85c30-10 am85c30-16
amd 7 am85c30 pin description bus timing and reset rd read (input; active low) this signal indicates a read operation and, when the scc is selected, enables the sccs bus drivers. during the interrupt acknowledge cycle, this signal gates the interrupt vector onto the bus if the scc is the highest pri- ority device requesting an interrupt. wr write (input; active low) when the scc is selected, this signal indicates a write operation. the coincidence of rd and wr is interpreted as a reset. channel clocks rtxca , rtxcb receive/transmit clocks (inputs; active low) these pins can be programmed in several different modes of operation. in each channel, rtxc may supply the receive clock, the transmit clock, the clock for the baud rate generator, or the clock of the digital phase- locked loop. these pins can also be programmed for use with the respective sync pins as a crystal oscilla- tor. the receive clock may be 1, 16, 32, or 64 times the data rate in asynchronous modes. trxca , trxcb transmit/receive clocks (inputs/outputs; active low) these pins can be programmed in several different modes of operation. trxc may supply the receive clock or the transmit clock in the input mode or supply the out- put of the digital phase-locked loop, the crystal oscilla- tor, the baud rate generator, or the transmit clock in the output mode. channel controls for modem, dma, or other ctsa , ctsb clear to send (inputs; active low) if these pins are programmed as auto enables, a low on these inputs enables their respective transmitters. if not programmed as auto enables, they may be used as general-purpose inputs. both inputs are schmitt-trigger buffered to accommodate slow rise-time inputs. the scc detects pulses on these inputs and may interrupt the cpu on both logic level transitions. dcda , dcdb data carrier detect (inputs; active low) these pins function as receiver enables if they are pro- grammed as auto enables; otherwise, they may be used as general-purpose input pins. both are schmitt- trigger buffered to accommodate slow rise-time signals. the scc detects pulses on these pins and may interrupt the cpu on both logic level transitions. dtr / reqa , dtr / reqb data terminal ready/request (outputs; active low) these outputs follow the inverted state programmed into the dtr bit in wr5. they can also be used as general-purpose outputs or as request lines for a dma controller. rtsa , rtsb request to send (outputs; active low) when the request to send (rts) bit in write register 5 is set, the rts signal goes low. when the rts bit is re- set in the asynchronous mode and auto enable is on, the signal goes high after the transmitter is empty. in sync mode, or in asynchronous mode with auto en- able off, the rts pins strictly follow the inverted state of the rts bit. both pins can be used as general-purpose outputs. in sdlc mode, the auto rts reset enhancement described later in this document brings rts high after the last 0 of the closing flag leaves the txd pin. synca , syncb synchronization (inputs/outputs; active low) these pins can act either as inputs, outputs, or part of the crystal oscillator circuit. in the asynchronous re- ceive mode (crystal oscillator option not selected), these pins are inputs similar to cts and dcd . in this mode, transitions on these lines affect the state of the sync/ hunt status bits in read register 0 but have no other function. in external synchronization mode with the crystal oscillator not selected, these lines also act as inputs. in this mode, sync must be driven low two receive clock cycles after the last bit in the sync character is received. character assembly begins on the rising edge of the receive clock immediately preceding the activa- tion of sync . in the internal synchronization mode (monosync and bisync) with the crystal oscillator not selected, these pins act as outputs and are active only during the part of the receive clock cycle in which sync characters are recognized. the sync condition is not latched, so these outputs are active each time a sync pattern is recognized (regardless of character boundaries). in sdlc mode, these pins act as outputs and are valid on receipt of a flag.
amd 8 am85c30 w / reqa , w / reqb wait/request (outputs; open drain when pro- grammed for a wait function, driven high or low when programmed for a request function) these dual-purpose outputs may be programmed as request lines for a dma controller or as wait lines to synchronize the cpu to the scc data rate. the reset state is wait. control a/ b channel a / channel b select (input) this signal selects the channel in which the read or write operation occurs. ce chip enable (input; active low) this signal selects the scc for a read or write operation. d/ c data / control select (input) this signal defines the type of information transferred to or from the scc. a high means data is transferred; a low indicates a command is transferred. data bus d 7 Cd 0 data bus (input/output; three state) these lines carry data and commands to and from the scc. interrupt iei interrupt enable in (input; active high) iei is used with ieo to form an interrupt daisy chain when there is more than one interrupt-driven device. a high iei indicates that no other higher priority device has an interrupt under service or is requesting an interrupt. ieo interrupt enable out (output; active high) ieo is high only if iei is high and the cpu is not servic- ing an scc interrupt or the scc is not requesting an interrupt (interrupt acknowledge cycle only). ieo is con- nected to the next lower priority devices iei input and thus inhibits interrupts from lower priority devices. int interrupt request (output; active low, open drain) this signal is activated when the scc requests an interrupt. intack interrupt acknowledge (input; active low) this signal indicates an active interrupt acknowledge cycle. during this cycle, the scc interrupt daisy chain settles. when rd becomes active, the scc places an interrupt vector on the data bus (if iei is high). intack is latched by the rising edge of pclk. serial data rxda, rxdb receive data (inputs; active high) these input signals receive serial data at standard ttl levels. txda, txdb transmit data (outputs; active high) these output signals transmit serial data at standard ttl levels. miscellaneous gnd ground pclk clock (input) this is the master scc clock used to synchronize inter- nal signals. pclk is not required to have any phase relationship with the master system clock. pclk is a ttl- level signal. maximum transmit rate is 1/4 pclk. v cc + 5 v power supply
amd 9 am85c30 architecture the escc internal structure includes two full-duplex channels, two 10 19 bit sdlc/hdlc frame status fifos, two baud rate generators, internal control and in- terrupt logic, and a bus interface to a non-multiplexed bus. associated with each channel are a number of read and write registers for mode control and status in- formation, as well as logic necessary to interface with modems or other external devices (see logic symbol). the logic for both channels provides formats, synchroni- zation, and validation for data transferred to and from the channel interface. the modem control inputs are monitored by the control logic under program control. all of the modem control signals are general-purpose in na- ture and can optionally be used for functions other than modem control. the register set for each channel includes ten control (write) registers, two sync character (write) registers, and four status (read) registers. in addition, each baud rate generator has two (read/write) registers for hold- ing the time constant that determines the baud rate. fi- nally, associated with the interrupt logic is a write register for the interrupt vector accessible through either channel, a write-only master interrupt control register, and three read registers: one containing the vector with status information (channel b only), one containing the vector without status (a only), and one containing the in- terrupt pending bits (a only). the registers for each channel are designated as follows: wr0Cwr15write registers 0 through 15. an addi- tional write register, wr7 prime (wr7 ), is available for enabling or disabling additional sdlc/hdlc enhance- ments if bit d 0 of wr15 is set. rr0Crr3, rr10, rr12, rr13, rr15read regis- ters 0 through 3, 10, 12, 13, and 15. if bit d 2 of wr15 is set, then two additional read regis- ters, rr6 and rr7, are available. these registers are used with the 10 19 bit frame status fifo. table 1 lists the functions assigned to each read and write register. the escc contains only one wr2 and wr9, but they can be accessed by either channel. all other registers are paired (one for each channel). channel b registers data control cpu bus vo internal control logic internal bus channel a registers interrupt control logic +5 v gnd pclk channel a channel b control logic transmitter receiver baud rate generator 10 19 bit frame status fifo interrupt control lines txda rxda rtxca trxca synca rtsa ctsa dcda rxdb rtxcb trxcb syncb rtsb ctsb dcdb 5 10216f-5 txdb 8 figure 1. block diagram of escc architecture
amd 10 am85c30 data path the transmit and receive data path illustrated in figure 2 is identical for both channels. the receiver has three 8-bit buffer registers in a fifo arrangement, in addition to the 8-bit receive shift register. this scheme creates additional time for the cpu to service an interrupt at the beginning of a block of high-speed data. incoming data are routed through one of several paths (data or crc) depending on the selected mode (the character length in asynchronous modes also determines the data path). the transmitter has an 8-bit transmit data buffer register loaded from the internal data bus and a 20-bit transmit shift register that can be loaded either from the sync- character registers or from the transmit data register. depending on the operational mode, outgoing data are routed through one of four main paths before they are transmitted from the transmit data output (txd). table 1. read and write register functions write register functions rr0 transmit/receive buffer status and external status rr1 special receive condition status (also 10 19 bit fifo frame reception status if wr15 bit d 2 is set) rr2 modified interrupt vector (channel b only) unmodified interrupt vector (channel a only) rr3 interrupt pending bits (channel a only) rr6 lsb byte count (14-bit counter) (if wr15 bit d 2 set) rr7 msb byte count (14-bit counter) and 10 19 bit fifo status (if wr15 bit d 2 is set) rr8 receive buffer rr10 miscellaneous xmtr, rcvr status rr12 lower byte of baud rate generator time constant rr13 upper byte of baud rate generator time constant rr15 external/status interrupt information wr0 command register, register pointers crc initialize, initialization commands for the various modes, shift right/shift left command wr1 interrupt conditions and data transfer mode definition wr2 interrupt vector (accessed through either channel) wr3 receive parameters and control wr4 transmit/receive miscellaneous parameters and modes wr5 transmit parameters and controls wr6 sync character or sdlc address field wr7 sync character or sdlc flag wr7 sdlc/hdlc enhancements (if bit d 0 of wr15 is set) wr8 transmit buffer wr9 master interrupt control and reset (accessed through either channel) wr10 miscellaneous transmitter/receiver control bits, data encoding wr11 clock mode control, rx and tx clock source wr12 lower byte of baud rate generator time constant wr13 upper byte of baud rate generator time constant wr14 miscellaneous control bits, dpll control wr15 external/status interrupt control read register functions write register functions
am85c30 11 amd
amd 12 am85c30 detailed description the functional capabilities of the escc can be de- scribed from two different points of view: as a data com- munications device, it transmits and receives data in a wide variety of data communications protocols; as a mi- croprocessor peripheral, it interacts with the cpu and provides vectored interrupts and handshaking signals. data communications capabilities the escc provides two independent full-duplex channels programmable for use in any common asynchronous or sync data-communication protocol. figure 3 and the following description briefly detail these protocols. asynchronous modes transmission and reception can be accomplished inde- pendently on each channel with 5 to 8 bits per character, plus optional even or odd parity. the transmitters can supply 1, 1 1/2, or 2 stop bits per character and can pro- vide a break output at any time. the receiver break- detection logic interrupts the cpu both at the start and at the end of a received break. reception is protected from spikes by a transient spike-rejection mechanism that checks the signal one-half a bit time after a low level is detected on the receive data input. if the low does not persist (as in the case of a transient), the character as- sembly process does not start. framing errors and overrun errors are detected and buffered together with the partial character on which they occur. vectored interrupts allow fast servicing of error conditions using dedicated routines. furthermore, a built-in checking process avoids the interpretation of framing error as a new start bit; a framing error results in the addition of one-half a bit time to the point at which the search for the next start bit begins. the escc does not require symmetric transmit and receive clock signalsa feature allowing use of the wide variety of clock sources. the transmitter and re- ceiver can handle data at a rate of 1, 1/16, 1/32, or 1/64 of the clock rate supplied to the receive and transmit clock inputs. in asynchronous modes, the sync pin may be programmed as an input used for functions, such as monitoring a ring indicator. synchronous modes the escc supports both byte-oriented and bit-oriented synchronous communication. sync byte-oriented pro- tocols can be handled in several modes, allowing char- acter synchronization with a 6-bit or 8-bit sync character (monosync), any 12-bit or 16-bit sync pat- tern (bisync), or with an external sync signal. leading sync characters can be removed without interrupting the cpu. 5- or 7-bit sync characters are detected with 8- or 16-bit patterns in the escc by overlapping the larger pattern across multiple incoming sync characters as shown in figure 4. crc checking for synchronous byte-oriented modes is delayed by one character time so that the cpu may dis- able crc checking on specific characters. this permits the implementation of protocols, such as ibm bisync. both crc-16 (x 16 + x 15 + x 2 + 1) and ccitt (x 16 + x 12 + x 5 + 1) error-checking polynomials are supported. either polynomial may be selected in bisync and mono-sync modes. users may preset the crc gen- erator and checker to all 1s or all 0s. the escc also pro- vides a feature that automatically transmits crc data when no other data are available for transmission. this allows for high-speed transmissions under dma control parity start stop marking line marking line asynchronous monosync bisync external sync sdlc/hdlc 25 sync data data crc 1 crc 2 sync sync data data crc 1 crc 2 data data crc 1 crc 2 signal flag address information flag crc 2 crc 1 data data data figure 3. scc protocols 10216f-7
amd 13 am85c30 sync data data sync sync data data 5 bits 8 bits 16 bits figure 4. detecting 5- or 7-bit synchronous characters 10216f-8 with no need for cpu intervention at the end of a mes- sage. when there are no data or crc to send in sync modes, the transmitter inserts 6-, 8-, or 16-bit sync characters, regardless of the programmed character length. the escc supports sync bit-oriented protocols, such as sdlc and hdlc, by performing automatic flag send- ing, zero-bit insertion, and crc generation. a special command can be used to abort a frame in transmission. at the end of a message, the escc automatically trans- mits the crc and trailing flag when the transmitter un- derruns. the transmitter may also be programmed to send an idle line consisting of continuous flag charac- ters or a steady marking condition. if a transmit underrun occurs in the middle of a mes- sage, an external/status interrupt warns the cpu of this status change so that an abort may be issued. the escc may also be programmed to send an abort itself in case of an underrun, relieving the cpu of this task. one to 8 bits per character can be sent allowing recep- tion of a message with no prior information about the character structure in the information field of a frame. the receiver automatically acquires synchronization on the leading flag of a frame in sdlc or hdlc and pro- vides a synchronization signal on the sync pin (an in- terrupt can also be programmed). the receiver can be programmed to search for frames addressed by a single byte (or 4 bits within a byte) of a user-selected address or to a global broadcast address. in this mode, frames not matching either the user-selected or broadcast ad- dress are ignored. the number of address bytes can be extended under software control. for receiving data, an interrupt on the first received character, or an interrupt on every character, or on special condition only (end-of- frame) can be selected. the receiver automatically de- letes all 0s inserted by the transmitter during character assembly. crc is also calculated and is automatically checked to validate frame transmission. at the end of transmission, the status of a received frame is available in the status registers. in sdlc mode, the escc must be programmed to use the sdlc crc polynomial, but the generator and checker may be preset to all 1s or all 0s. the crc is inverted before transmission and the receiver checks against the bit pattern 0001110100001111. nrz, nrzi or fm coding may be used in any 1x mode. the parity options available in asynchronous modes are available in synchronous modes. the escc can be conveniently used under dma control to provide high-speed reception or transmission. in re- ception, for example, the escc can interrupt the cpu when the first character of a message is received. the cpu then enables the dma to transfer the message to memory. the escc then issues an end-of-frame inter- rupt and the cpu can check the status of the received message. thus, the cpu is freed for other service while the message is being received. the cpu may also en- able the dma first and have the escc interrupt only on end-of-frame. this procedure allows all data to be trans- ferred via the dma. sdlc loop mode the escc supports sdlc loop mode in addition to normal sdlc. in a sdlc loop, there is a primary con- troller station that manages the message traffic flow and any number of secondary stations. in sdlc loop mode, the escc performs the functions of a secondary station while an escc operating in regular sdlc mode can act as a controller (figure 5). controller secondary #1 secondary #2 secondary #3 secondary #4 figure 5. a sdlc loop 10216f-9 a secondary station in a sdlc loop is always listening to the messages being sent around the loop and, in fact, must pass these messages to the rest of the loop by retransmitting them with a 1-bit time delay. the sec- ondary station can place its own message on the loop only at specific times. the controller signals that secon- dary stations may transmit messages by sending a spe- cial character, called an eop (end of poll), around the loop. the eop character is the bit pattern 11111110. because of zero insertion during messages, this bit pat- tern is unique and easily recognized.
amd 14 am85c30 when a secondary station has a message to transmit and recognizes an eop on the line, it changes the last binary 1 of the eop to a 0 before transmission. this has the effect of turning the eop into a flag sequence. the secondary station now places its message on the loop and terminates the message with an eop. any secon- dary stations farther down the loop with messages to transmit can then append their messages to the mes- sage of the first secondary station by the same process. any secondary stations without messages to send merely echo the incoming messages and are prohibited from placing messages on the loop (except upon recog- nizing an eop). sdlc loop mode is a programmable option in the escc. nrz, nrzi, and fm coding may all be used in sdlc loop mode. baud rate generator each channel in the escc contains a programmable baud rate generator. each generator consists of two 8-bit time constant registers that form a 16-bit time con- stant, a 16-bit down counter, and a flip-flop on the output producing a square wave. on start-up, the flip-flop on the output is set in a high state, the value in the time con- stant register is loaded into the counter, and the counter starts counting down. the output of the baud rate gen- erator toggles upon reaching zero; the value in the time constant register is loaded into the counter, and the process is repeated. the time constant may be changed at any time, but the new value does not take effect until the next load of the counter. the output of the baud rate generator may be used as either the transmit clock, the receive clock, or both. it can also drive the digital phase-locked loop (see next section). if the receive clock or transmit clock is not programmed to come from the trxc pin, the output of the baud rate generator may be echoed out via the trxc pin. the following formula relates the time constant to the baud rate where pclk or rtxc is the baud rate genera- tor input frequency in hz. the clock mode is x1, x16, x32, or x64 as selected in write register 4, bits d 6 and d 7 . synchronous operation modes should select x1 and asynchronous should select x16, x32, or x64. time constant = pclk or rtxc frequency 2 (baud rate)(clock mode) C 2 the following formula relates the time constant to the baud rate. the baud rate is in bits/second. baud rate = 2 (clock mode) (time constant + 2) pclk or rtxc frequency time constant values for standard baud rates at br clock = 3.9936 mhz rate (baud) time constant (decimal/hex notation) error 19200 9600 7200 4800 3600 2400 2000 1800 1200 600 300 150 134.5 110 75 50 102 206 275 414 553 830 996 1107 1662 3326 6654 13310 14844 18151 26622 39934 (0066) (00ce) (0113) (019e) (0229) (033e) (03e4) (0453) (067e) (0cfe) (19fe) (33fe) (39fc) (46e7) (67fe) (98fe) 0 0 0.12% 0 0.06% 0 0.04% 0.03% 0 0 0 0 0.0007% 0.0015% 0 0 digital phase-locked loop the escc contains a digital phase-locked loop (dpll) to recover clock information from a data stream with nrzi or fm encoding. the dpll is driven by a clock that is nominally 32 (nrzi) or 16 (fm) times the data rate. the dpll uses this clock, along with the data stream, to construct a clock for the data. this clock may then be used as the scc receive clock, the transmit clock, or both. for nrzi encoding, the dpll counts the 32x clock to create nominal bit times. as the 32x clock is counted, the dpll is searching the incoming data stream for edges (either 1/0 or 0/1). as long as no transitions are detected, the dpll output will be free running and its in- put clock source will be divided by 32, producing an out- put clock without any phase jitter. upon detecting a transition the dpll will adjust its clock output (during the next counting cycle) by adding or subtracting a count of 1, thus producing a terminal count closer to the center of the bit cell. the adding or subtracting of a count of 1 will produce a phase jitter of 5.63 on the output of the dpll. because the sccs dpll uses both edges of the incoming signal to compare with its clock source, the mark-space ratio (50%) of the incoming signal should not deviate by more than 1.5% if proper locking is to occur. for fm encoding, the dpll still counts from 0 to 31, but with a cycle corresponding to two bit times. when the dpll is locked, the clock edges in the data stream should occur between counts 15 and 16 and between
amd 15 am85c30 counts 31 and 0. the dpll looks for edges only during a time centered on the 15/16 counting transition. the 32x clock for the dpll can be programmed to come from either the rtxc input or the output of the baud rate generator. the dpll output may be pro- grammed to be echoed out of the scc via the trxc pin (if this pin is not being used as an input). crystal oscillator when using a crystal oscillator to supply the receive or transmit clocks to a channel of the scc, the user should: 1. select a crystal oscillator that satisfies the following specifications: 30 ppm @ 25 c 50 ppm over temperatures of C20 to 70 c 5 ppm/yr aging 5-mw drive level 2. place crystal across rtxc and sync pins. 3. place 30-pf capacitors to ground from both rtxc and sync pins. 4. set bit d 7 of wr11 to 1. data encoding the escc may be programmed to encode and decode the serial data in four different ways (figure 6). in nrz encoding, a 1 is represented by a high level, and a 0 is represented by a low level. in nrzi encoding, a 1 is rep- resented by no change in level, and a 0 is represented by a change in level. in fm 1 (more properly, biphase mark), a transition occurs at the beginning of every bit cell. a 1 is represented by an additional transition at the center of the bit cell, and a 0 is represented by no additional transition at the center of the bit cell. in fm 0 (biphase space), a transition occurs at the beginning of every bit cell. a 0 is represented by an additional transi- tion at the center of the bit cell, and a 1 is represented by no additional transition at the center of the bit cell. in ad- dition to these four methods, the escc can be used to decode manchester (biphase level) data by using the dpll in the fm mode and programming the receiver for nrz data. manchester encoding always produces a transition at the center of the bit cell. if the transition is 0/1, the bit is a 0. if the transition is 1/0, the bit is a 1. auto echo and local loopback the escc is capable of automatically echoing every- thing it receives. this feature is useful mainly in asyn- chronous modes but works in sync and sdlc modes as well. in auto echo mode, txd is rxd. auto echo mode can be used with nrzi or fm encoding with no ad- ditional delay, because the data stream is not decoded before retransmission. in auto echo mode, the cts in- put is ignored as a transmitter enable (although transi- tions on this input can still cause interrupts if programmed to do so). in this mode, the transmitter is actually bypassed, and the programmer is responsible for disabling transmitter interrupts and wait / request on transmit. the escc is also capable of local loopback. in this mode, txd is rxd just as in auto echo mode. however, in local loopback mode, the internal transmit data is tied to the internal receive data, and rxd is ignored (ex- cept to be echoed out via txd). the cts and dcd in- puts are also ignored as transmit and receive enables. however, transitions on these inputs can still cause in- terrupts. local loopback works in asynchronous, sync, and sdlc modes with nrz, nrzi, or fm coding of the data stream. 1 1 001 0 data nrz nrzi (biphase mark) (biphase mark) manchester bit cell level high = 1 low = 0 no change = 1 change = 0 bit center transition transition = 1 no transition = 0 no transition = 1 transition = 0 high low = 1 low high = 0 figure 6. data encoding methods fm 1 fm 0 10216f-10
amd 16 am85c30 i/o interface capabilities the escc offers the choice of polling, interrupt (vec- tored or nonvectored), and block transfer modes to transfer data, status, and control information to and from the cpu. the block transfer mode can be implemented under cpu or dma control. polling all interrupts are disabled. three status registers in the escc are automatically updated whenever any func- tion is performed. for example, end-of-frame in sdlc mode sets a bit in one of these status registers. the idea behind polling is for the cpu to periodically read a status register until the register contents indicate the need for data to be transferred. only one register needs to be read; depending on its contents, the cpu either writes data, reads data, or continues. two bits in the register indicate the need for data transfer. an alternative is a poll of the interrupt pending register to determine the source of an interrupt. the status for both channels re- sides in one register. interrupts when an escc responds to an interrupt acknowledge signal (intack) from the cpu, an interrupt vector may be placed on the data bus. this vector is written in wr2 and may be read in rr2a or rr2b (figures 8 and 9). to speed interrupt response time, the escc can modify 3 bits in this vector to indicate status. if the vector is read in channel a, status is never included; if it is read in channel b, status is always included. each of the six sources of interrupts in the escc (trans- mit, receive, and external/status interrupts in both channels) has 3 bits associated with the interrupt source: interrupt pending (ip), interrupt under service (ius), and interrupt enable (ie). operation of the ie bit is straightforward. if the ie bit is set for a given interrupt source, then that source can request interrupts. the ex- ception is when the mie (master interrupt enable) bit in wr9 is reset and no interrupts may be requested. the ie bits are write-only. the other 2 bits are related to the z-bus interrupt priority chain (figure 7). as a z-bus peripheral, the escc may request an interrupt only when no higher priority device is requesting one, for example, when iei is high. if the device in question requests an interrupt, it pulls down int . the cpu then responds with intack , and the in- terrupting device places the vector on the a/d bus. in the scc, the ip bit signals a need for interrupt servic- ing. when an ip bit is set to 1 and the iei input is high, the int output is pulled low, requesting an interrupt. in the escc, if the ie bit is set for an interrupt, then the ip for that source can never be set. the ip bits are readable in rr3a. the ius bits signal that an interrupt request is being serviced. if an ius is set, all interrupt sources of lower priority in the escc and external to the escc are pre- vented from requesting interrupts. the internal interrupt sources are inhibited by the state of the internal daisy chain, while lower priority devices are inhibited by the ieo output of the escc being pulled low and propa- gated to subsequent peripherals. an ius bit is set during an interrupt acknowledge cycle if there are no higher priority devices requesting interrupts. there are three types of interrupts: transmit, receive, and external/status. each interrupt type is enabled un- der program control with channel a having higher prior- ity than channel b, and with receive, transmit, and external/status interrupts prioritized in that order within each channel. when the transmit interrupt is enabled, the cpu is interrupted when the transmit buffer be- comes empty. (this implies that the transmitter must have had a data character written into it so that it can be- come empty.) when enabled, the receive can interrupt the cpu in one of three ways: interrupt on first receive character or special receive condition interrupt on all receive characters or special receive condition interrupt on special receive condition only figure 7. z-bus interrupt schedule peripheral iei ad 7 Cad 0 int intack ieo peripheral peripheral iei ad 7 Cad 0 int intack ieo iei ad 7 Cad 0 int intack +5 v +5 v d 7 Cd 0 ad 7 Cad 0 int intack 10216f-11
amd 17 am85c30 interrupt on first character or special condition and in- terrupt on special condition only are typically used with the block transfer mode. a special receive condition is one of the following: receiver overrun, framing error in asynchronous mode, end-of-frame in sdlc mode, and optionally, a parity error. the special receive condition interrupt is different from an ordinary receive character available interrupt only in the status placed in the vector during the interrupt acknowledge cycle. in interrupt on first receive character, an interrupt can occur from special receive conditions any time after the first receive character interrupt. the main function of the external/status interrupt is to monitor the signal transitions of the cts , dcd , and sync pins; however, an external/status interrupt is also caused by a transmit underrun condition, a zero count in the baud rate generator, the detection of a break (asynchronous mode), abort (sdlc mode), or eop (sdlc loop mode) sequence in the data stream. the interrupt caused by the abort or eop has a special feature allowing the escc to interrupt when the abort or eop sequence is detected or terminated. this feature facilitates the proper termination of the current message, correct initialization of the next message, and the accurate timing of the abort condition in external logic in sdlc mode. in sdlc loop mode, this feature allows secondary stations to recognize the wishes of the primary station to regain control of the loop during a poll sequence. cpu/dma block transfer the scc provides a block transfer mode to accommo- date cpu block transfer functions and dma controllers. the block transfer mode uses the wait / request output in conjunction with the wait/request bits in wr1. the wait / request output can be defined under soft- ware control as a wait line in the cpu block transfer mode or as a request line in the dma block transfer mode. to a dma controller, the escc request output indi- cates that the escc is ready to transfer data to or from memory. to the cpu, the wait line indicates that the scc is not ready to transfer data, thereby requesting that the cpu extend the i/o cycle. the dtr / request can be used as the transmit request line, thus allowing full-duplex operation under dma control. programming information each channel has fifteen write registers that are indi- vidually programmed from the system bus to configure the functional personality of each channel. each chan- nel also has eight read registers from which the system can read status, baud rate, or interrupt information. on the am85c30, only four data registers (read and write for channels a and b) are directly selected by a high on the d/ c input and the appropriate levels on the rd , wr , and a/ b pins. all other registers are addressed indirectly by the content of write register 0 in conjunc- tion with a low on the d/ c input and the appropriate lev- els on the rd , wr , and a/ b pins. if bit d 3 in wr0 is 1 and bits 5 and 6 are 0, then bits 0, 1, and 2 address the higher registers 8 through 15. if bits 4, 5, and 6 contain a differ- ent code, bits 0, 1, and 2 address the lower registers 0 through 7 as shown in table 2. writing to or reading from any register except rr0, wr0, and the data registers thus involves two operations: first, write the appropriate code into wr0, then follow this by a write or read operation on the register thus specified. bits 0 through 4 in wr0 are automatically cleared after this operation, so that wr0 then points to wr0 or rr0 again. channel a/channel b selection is made by the a/ b input (high = a, low = b). the system program first issues a series of commands to initialize the basic mode of operation. this is followed by other commands to qualify conditions within the se- lected mode. for example, the asynchronous mode, character length, clock rate, number of stop bits, even or odd parity might be set first. then the interrupt mode would be set and, finally, receiver or transmitter enable.
amd 18 am85c30 table 2. register addressing point high d 2 , d 1 , d 0 write read d / c code in wr0: in wr0: register register high either way x x x data data low not true 0 0 0 0 0 low not true 0 0 1 1 1 low not true 0 1 0 2 2 low not true 0 1 1 3 3 low not true 1 0 0 4 (0) low not true 1 0 1 5 (1) low not true 1 1 0 6 (2) low not true 1 1 1 7 (3) low true 0 0 0 data data low true 0 0 1 9 C low true 0 1 0 10 10 low true 0 1 1 11 (15) low true 1 0 0 12 12 low true 1 0 1 13 13 low true 1 1 0 14 (10) low true 1 1 1 15 15 read registers the escc contains eight read registers [actually nine, counting the receive buffer (rr8) in each channel]. four of these may be read to obtain status information (rr0, rr1, rr10, and rr15). two registers (rr12 and rr13) may be read to learn the baud rate generator time constant. rr2 contains either the unmodified inter- rupt vector (channel a) or the vector modified by status information (channel b). rr3 contains the interrupt pending (ip) bits (channel a). in addition, if bit d 2 of wr15 is set, rr6 and rr7 are available for providing frame status from the 10 19 bit frame status fifo. figure 8 shows the formats for each read register. the status bits of rr0 and rr1 are carefully grouped to simplify status monitoring, for example, when the inter- rupt vector indicates a special receive condition interrupt, all the appropriate error bits can be read from a single register (rr1). please refer to am85c30 technical manual for detailed descriptions of the read registers. write registers the escc contains 15 write registers (16 counting wr8, the transmit buffer) in each channel. these write registers are programmed separately to configure the functional personality of the channels. two registers (wr2 and wr9) are shared by the two channels that can be accessed through either of them. wr2 contains the interrupt vector for both channels, while wr9 con- tains the interrupt control bits. in addition, if bit d 0 of wr15 is set, write register 7 prime (wr7 ) is available for programming additional sdlc/hdlc enhance- ments. when bit d 0 of wr15 is set, executing a write to wr7 actually writes to wr7 to further enhance the functional personality of each channel. figure 8 shows the format of each write register.
amd 19 am85c30 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 rx character available zero count tx buffer empty dcd sync hunt cts tx underrun/eom break abort read register 0 read register 3 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 channel b ext stat ip* channel b tx ip* channel b rx ip* channel a ext stat ip* channel a tx ip* channel a rx ip* 0 0 *always 0 in b channel read register 1 read register 6 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 all sent residue code 2 residue code 1 residue code 0 parity error rx overrun error crc framing error end-of-frame (sdlc) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 bc0 bc1 bc2 bc3 bc4 bc5 bc6 bc7 lsb byte count read register 2 read register 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 v0 v1 v2 v3 v4 v5 v6 v7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10216f-12 interrupt vector* *modified in b channel bc8 bc9 bc10 bc11 bc12 bc13 fda* foy** 10 19 bit fifo status 14-bit msb byte count 14-bit *fifo data available status **fifo overflow status figure 8. read register bit functions
amd 20 am85c30 read register 10 read register 13 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 on loop 0 0 loop sending 0 two clocks missing one clock missing d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read register 12 read register 15 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 tc 0 tc 1 tc 2 tc 3 tc 4 tc 5 tc 6 tc 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 *added enhancement sdlc/hdlc enhancement status* zero count ie 10 19 bit fifo enable/disable* dcd ie sync hunt ie cts ie tx underrun/eom ie break/abort ie lower byte of time constant upper byte of time constant tc 8 tc 9 tc 10 tc 11 tc 12 tc 13 tc 14 tc 15 figure 8. read register bit functions (continued) 10216f-12 (concluded) write register 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 null code point high register group reset ext/status interrupts send abort enable int on next rx character reset tx int pending error reset reset highest ius register null code reset rx crc checker reset tx crc generator reset tx underrun/eom latch figure 9. write register bit functions 10216f-13
amd 21 am85c30 0 0 1 1 0 1 0 1 0 0 1 1 write register 1 write register 4 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ext int enable tx int enable parity is special condition d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 write register 2 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 v0 v1 v2 v3 v4 v5 v6 v7 interrupt vector* write register 6 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 write register 5 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 tx crc enable rts sdlc /crc-16 tx enable send break 0 0 1 1 0 1 0 1 write register 3 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 rx enable sync character load inhibit address search mode (sdlc) rx crc enable enter hunt mode auto enable 0 0 1 1 0 1 0 1 parity enable parity even/ odd sync modes enable 1 stop bit/character 1 1/2 stop bits/character 2 stop bits/character 8-bit sync character 16-bit sync character sdlc mode (01111110 flag) external sync mode x1 clock mode x16 clock mode x32 clock mode x64 clock mode rx int disable rx int on first character or special condition int on all rx characters or special condition rx int on special condition only wait/dma request on receive/transmit wait/dma request function wait/dma request enable tx 5 bits (or less)/character tx 7 bits/character tx 6 bits/character tx 8 bits/character dtr rx 5 bits/character rx 7 bits/character rx 6 bits/character rx 8 bits/character sync 7 sync 1 sync 7 sync 3 adr 7 adr 7 sync 6 sync 0 sync 6 sync 2 adr 6 adr 6 sync 5 sync 5 sync 5 sync 1 adr 5 adr 5 sync 4 sync 4 sync 4 sync 0 adr 4 adr 4 sync 3 sync 3 sync 3 1 adr 3 1 sync 2 sync 2 sync 2 1 adr 2 1 sync 1 sync 1 sync 1 1 adr 1 1 sync 0 sync 0 sync 0 1 adr 0 1 monosync 8 bits monosync 8 bits bisync 16 bits bisync 12 bits sdlc sdlc (address 0) figure 9. write register bit functions (continued) 10216f-13
amd 22 am85c30 write register 11 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 write register 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 auto tx flag auto eom latch reset auto rts txd pulled high in sdlc nrzi mode fast dtr/req mode crc check bytes completely received extended read enable must be set to 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 write register 9 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 vis nv dlc mie status high/ status low interrupt masking without intack* 0 0 1 1 0 1 0 1 no reset channel reset b channel reset a force hardware reset d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sync 7 sync 5 sync 5 sync 11 0 sync 6 sync 4 sync 14 sync 10 1 sync 5 sync 3 sync 13 sync 9 1 sync 4 sync 2 sync 12 sync 8 1 sync 3 sync 1 sync 11 sync 7 1 sync 2 sync 0 sync 10 sync 6 1 sync 1 1 sync 9 sync 5 1 sync 0 1 sync 8 sync 4 0 monosync 8 bits monosync 8 bits bisync 16 bits bisync 12 bits sdlc write register 7 *added enhancement trxc o/i trxc out = xtal output trxc out = transmit clock trxc out = br generator output trxc out = dpll output transmit clock = rtxc pin transmit clock = trxc pin transmit clock = br generator output transmit clock = dpll output receive clock = rtxc pin receive clock = trxc pin receive clock = br generator output receive clock = dpll output rtxc xtal/ no xtal figure 9. write register bit functions (continued) 10216f-13
amd 23 am85c30 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 write register 12 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 tc 0 tc 1 tc 2 tc 3 tc 4 tc 5 tc 6 tc 7 lower byte of time constant write register 14 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 br generator enable br generator source dtr /request function auto echo local loopback write register 10 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 6-bit/ 8-bit sync loop mode abort/ flag on underrun mark/ flag idle go active on roll 0 0 1 1 0 1 0 1 nrz nrzi fm1 (transition = 1) fm0 (transition = 0) crc preset 1 or 0 write register 13 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 tc 8 tc 9 tc 10 tc 11 tc 12 tc 13 tc 14 tc 15 upper byte of time constant null command enter search mode reset missing clock disable dpll set source = br generator set source = rtxc set fm mode set nrzi mode write register 15 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sdlc/hdlc enhancements enable* zero count ie 10 19 bit fifo enable* dcd ie sync/hunt ie cts ie tx underrun/eom ie break/abort ie * added enhancement figure 9. write register bit functions (continued) 10216f-13 (concluded) am85c30 timing the escc generates internal control signals from wr and rd that are related to pclk. since pclk has no phase relationship with wr and rd , the circuitry gener- ating these internal control signals must provide time for metastable conditions to disappear. this gives rise to a recovery time related to pclk. the recovery time ap- plies only between bus transactions involving the escc. the recovery time required for proper operation is specified from the falling edge of wr or rd in the first transaction involving the escc, to the falling edge of wr or rd in the second transaction involving the escc. this time must be at least 3 1/2 pclk regardless of which register or channel is being accessed. read cycle timing figure 10 illustrates read cycle timing. addresses on a/ b and d/ c and the status on intack must remain sta- ble throughout the cycle. if ce falls after rd falls or if it rises before rd rises, the effective rd is shortened. write cycle timing figure 11 illustrates write cycle timing. addresses on a/ b and d/ c and the status on intack must remain stable throughout the cycle. if ce falls after wr falls or if it rises before wr rises, the effective wr is shortened. data must be valid before the rising edge of wr .
amd 24 am85c30 interrupt acknowledge cycle timing no tag illustrates interrupt acknowledge cycle timing. between the time intack goes low and the falling edge of rd , the internal and external iei/ieo daisy chains settle. if there is an interrupt pending in the escc and iei is high when rd falls, the acknowledge cycle is intended for the scc. in this case, the escc may be programmed to respond to rd low by placing its inter- rupt vector on d 7 Cd 0 ; it then sets the appropriate inter- rupt-under-service latch internally. address valid data valid a/ b , d/ c intack ce wr d 7 Cd 0 figure 10. read cycle timing 10216f-14 address valid data valid a/ b , d/ c intack ce wr d 7 Cd 0 figure 11. write cycle timing 10216f-15 vector intack rd d 7 Cd 0 figure 12. interrupt acknowledge cycle timing 10216f-16
amd 25 am85c30 fifo fifo enhancements when used with a dma controller, the am85c30 frame status fifo enhancement maximizes the esccs abil- ity to receive high-speed back-to-back sdlc messages while minimizing frame overruns due to cpu latencies in responding to interrupts. additional logic was added to the industry-standard nmos scc consisting of a 10-deep by 19-bit status fifo, a 14-bit receive byte counter, and control logic as shown in figure 13. the 10 19 bit status fifo is sepa- rate from the existing 3-byte receive data and error fifos. when the enhancement is enabled, the status in read register 1 (rr1) and byte count for the sdlc frame will be stored in the 10 19 bit status fifo. this allows the dma controller to transfer the next frame into memory while the cpu verifies that the message was properly received. summarizing the operation, data is received, assem- bled, and loaded into the 3-byte receive fifo before be- ing transferred to memory by the dma controller. when a flag is received at the end of an sdlc frame, the frame byte count from the 14-bit counter and 5 status bits are loaded into the status fifo for verification by the cpu. the crc checker is automatically reset in preparation for the next frame, which can begin immediately. since the byte count and status are saved for each frame, the message integrity can be verified at a later time. status information for up to 10 frames can be stored before a status fifo overrun could occur. if receive interrupts are enabled while the 10 19 fifo is enabled, an sdlc end-of-frame special condition will 6-bit mux residue bits(3) overrun crc error 10 19 bit fifo array 14 bits 6 bits tail pointer 4-bit counter 14-bit byte counter head pointer 4-bit counter 5 bits 6 bits 8 bits bits 0C5 6 bits 2 bits rr1 rr7 bit 6 bit 7 rr6 fifo enable reset on flag detect increment on byte det enable count in sdlc end-of-frame signal status read comp eof = 1 interface to scc over equal byte counter contains 14 bits for a 16-kb maximum count fifo data available status bit status bit set to 1 when reading from fifo fifo overflow status bit msb of rr(7) is set on status fifo overflow in sdlc mode, the following definitions apply: all sent bypasses mux and equals contents of scc status register. parity bits bypass mux and do the same. eof is set to 1 whenever reading from the fifo. wr(15) bit 2 set enables status fifo rr1 4-bit comparator scc status reg (existing) figure 13. scc status register modifications 10216f-17 en
amd 26 am85c30 not lock the 3-byte receive data fifo. an sdlc end-of-frame still locks the 3-byte receive data fifo in interrupt on first receive character or special condi- tion and interrupt on special condition only modes when the 10 19 fifo is disabled. this feature allows the 10 19 sdlc fifo to accept multiple sdlc frames without cpu intervention at the end of each frame. fifo detail for a better understanding of details of the fifo opera- tion, refer to the block diagram contained in figure 13. enable/disable this fifo is implemented so that it is enabled when wr15 bit 2 is set and the escc is in the sdlc/hdlc mode, otherwise the status register contents bypass the fifo and go directly to the bus interface (the fifo pointer logic is reset either when disabled or via a chan- nel or power-on reset). when the fifo mode is dis- abled, the escc is completely downward-compatible with the nmos am8530. the fifo mode is disabled on power-up (wr15 bit 2 is set to 0 on reset). the effects of backward compatibility on the register set are that rr4 is an image of rr0, rr5 is an image of rr1, rr6 is an image of rr2, and rr7 is an image of rr3. for the de- tails of the added registers, refer to figure 15. the status of the fifo enable signal can be obtained by reading rr15 bit 2. if the fifo is enabled, the bit will be set to 1; otherwise, it will be reset. read operation when wr15 bit 2 is set and the fifo is not empty, the next read to status register rr1 or the additional regis- ters rr7 and rr6 will actually be from the fifo. read- ing status register rr1 causes one location of the fifo to be emptied, so status should be read after reading the byte count, otherwise the count will be incorrect. before the fifo underflows, it is disabled. in this case, the mul- tiplexer is switched to allow status to be read directly from the status register, and reads from rr7 and rr6 will contain bits that are undefined. bit 6 of rr7 (fifo data available) can be used to determine if status data is coming from the fifo or directly from the status regis- ter, since it is set to 1 whenever the fifo is not empty. because not all status bits are stored in the fifo, the all sent, parity, and eof bits will bypass the fifo. the status bits sent through the fifo will be residue bits (3), overrun, and crc error. the sequence for proper operation of the byte count and fifo logic is to read the registers in the following order, rr7, rr6, and rr1 (reading rr6 is optional). addi- tional logic prevents the fifo from being emptied by multiple reads from rr1. the read from rr7 latches the fifo empty/full status bit (bit 6) and steers the status multiplexer to read from the scc megacell instead of the status fifo (since the status fifo is empty). the read from rr1 allows an entry to be read from the fifo (if the fifo was empty, logic is added to prevent a fifo underflow condition). write operation when the end of an sdlc frame (eof) has been re- ceived and the fifo is enabled, the contents of the status and byte-count registers are loaded into the fifo. the eof signal is used to increment the fifo. if the fifo overflows, the msb of rr7 (fifo overflow) is set to indicate the overflow. this bit and the fifo control logic are reset by disabling and reenabling the fifo control bit (wr15 bit 2). for details of fifo control tim- ing during an sdlc frame, refer to figure 14. byte counter detail the 14-bit byte counter allows for packets up to 16k bytes to be received. for a better understanding of its operation, refer to figures 13 and 14. f addddccf byte count data stream internal byte strobe increments counter internal byte strobe increments counter dont load counter on 1st flag reset byte counter here reset byte counter load counter into fifo and increment ptr reset byte counter reset byte counter load counter into fifo and increment ptr f : flag a : address field d : data c : control field key 0 1234567 0 1234567 f addddccf figure 14. sdlc byte counting detail 10216f-18
amd 27 am85c30 7 65432 10 foy fda bc bc bc bc bc bc 13 12 11 10 9 8 rr7 fifo data available status 1 = status reads will come from fifo 0 = status reads will come from scc fifo overflow status 1 = fifo overflowed during operation 0 = normal bc bc bc bc bc bc bc bc rr6 read from fifo lsb byte count rr15 enh fen status fifo enable control bit 1 = status and byte count will be 0= status will not be held (scc emulation mode) held in the status fifo until read = no change from nmos scc dfn 7 65432 10 7 65432 10 7 65432 10 enh: sdlc/hdlc enhancement status 1 = enhancements enabled 0 = enhancements disabled figure 15. scc additional registers 10216f-19 enable the byte counter is enabled when the scc is in the sdlc/hdlc mode and wr15 bit 2 is set to 1. reset the byte counter is reset whenever an sdlc flag char- acter is received. the reset is timed so that the contents of the byte counter are successfully written into the fifo. increment the byte counter is incremented by writes to the data fifo. the counter represents the number of bytes re- ceived by the scc, rather than the number of bytes transferred from the scc. (these counts may differ by up to the number of bytes in the receive data fifo con- tained in the scc.) am85c30 sdlc/hdlc enhancement register access sdlc/hdlc enhancements on the am85c30 are en- abled or disabled via bits d 2 or d 0 in wr15. bit d 2 deter- mines whether or not the 10 19 bit sdlc/hdlc frame status fifo is enabled while bit d 0 determines whether or not other enhancements are enabled via wr7 . table 3 shows what functions on the am85c30 are enabled when these bits are set. when bit d 2 of wr15 is set to 1, two additional registers (rr6 and rr7) per channel specific to the 10 19 bit frame status fifo are made available. the am85c30 register map when this function is enabled is shown in table 4. bit d 0 of wr15 determines whether or not other en- hancements pertinent only to sdlc/hdlc mode opera- tion are available for programming via wr7 as shown below. write register 7 prime (wr7 ) can be written to when bit d 0 of wr15 is set to 1. when this bit is set, writ- ing to wr7 (flag register) actually writes to wr7 . if bit d 6 of this register is set to 1, previously unreadable reg- isters wr3, wr4, wr5, and wr10 are readable by the pro-cessor. in addition, wr7 is also readable by having this bit set. wr3 is read when a bogus rr9 register is accessed during a read cycle. wr10 is read by access- ing rr11, and wr7 is accessed by executing a read to rr14. the am85c30 register map with bit d 0 of wr15 and bit d 6 of wr7 set is shown in table 5. if both bits d 0 and d 2 of wr15 are set to 1 and d 6 of wr7 is set to 1, then the am85c30 register map is as shown in table 6.
amd 28 am85c30 table 3. enhancement options wr15 bit d 2 wr15 bit d 0 wr7 bit d 6 10 19 bit sdlc/hdlc extended functions fifo enabled enhancement enabled read enabled enabled 10x10 19 bit fifo enhancement enabled only 0 1 0 sdlc/hdlc enhancements enabled only sdlc/hdlc enhancements 0 1 1 enabled with extended read enabled 10 19 bit fifo and 1 1 0 sdlc/hdlc enhancements enabled 10 19 bit fifo and 1 1 1 sdlc/hdlc enhancements with extended read enabled table 4. 10 19 bit fifo enabled a/ b pnt 2 pnt 1 pnt 0 write read 0 0 0 0 wr0b rr0b 0 0 0 1 wr1b rr1b 0 0 1 0 wr2 rr2b 0 0 1 1 wr3b rr3b 0 1 0 0 wr4b (rr0b) 0 1 0 1 wr5b (rr1b) 0 1 1 0 wr6b rr6b 0 1 1 1 wr7b rr7b 1 0 0 0 wr0a rr0a 1 0 0 1 wr1a rr1a 1 0 1 0 wr2 rr2a 1 0 1 1 wr3a rr3a 1 1 0 0 wr4a (rr0a) 1 1 0 1 wr5a (rr1a) 1 1 1 0 wr6a rr6a 1 1 1 1 wr7a rr7a with the point high command: a/ b pnt 2 pnt 1 pnt 0 write read 0 0 0 0 wr8b rr8b 0 0 0 1 wr9 rr13b 0 0 1 0 wr10b rr10b 0 0 1 1 wr11b (rr15b) 0 1 0 0 wr12b rr12b 0 1 0 1 wr13b rr13b 0 1 1 0 wr14b (rr10b) 0 1 1 1 wr15b rr15b 1 0 0 0 wr8a rr8a 1 0 0 1 wr9 (rr13a) 1 0 1 0 wr10a rr10a 1 0 1 1 wr11a (rr15a) 1 1 0 0 wr12a rr12a 1 1 0 1 wr13a rr13a 1 1 1 0 wr14a (rr10a) 1 1 1 1 wr15a rr15a
amd 29 am85c30 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 wr7 sdlc/hdlc programmable enhancements* sdlc/hdlc auto rts turnoff sdlc/hdlc auto eom reset sdlc/hdlc auto tx flag force txd high dtr / req fast mode rx comp. crc ext. read enable must be set to 0 *note: options 3, 4, 5, and 6 may be used regardless of whether sdlc/hdlc mode is selected. table 5. sdlc/hdlc enhancements enabled a/ b pnt 2 pnt 1 pnt 0 write read 0 0 0 0 wr0b rr0b 0 0 0 1 wr1b rr1b 0 0 1 0 wr2 rr2b 0 0 1 1 wr3b rr3b 0 1 0 0 wr4b rr4b (wr4b) 0 1 0 1 wr5b rr5b (wr5b) 0 1 1 0 wr6b (rr2b) 0 1 1 1 wr7b (rr3b) 1 0 0 0 wr0a rr0a 1 0 0 1 wr1a rr1a 1 0 1 0 wr2 rr2a 1 0 1 1 wr3a rr3a 1 1 0 0 wr4a rr4a (wr4a) 1 1 0 1 wr5a rr5a (wr5a) 1 1 1 0 wr6a (rr2a) 1 1 1 1 wr7a (rr3a) with the point high command: a/ b pnt 2 pnt 1 pnt 0 write read 0 0 0 0 wr8b rr8b 0 0 0 1 wr9 rr9 (wr3b) 0 0 1 0 wr10b rr10b 0 0 1 1 wr11b rr11b (wr10b) 0 1 0 0 wr12b rr12b 0 1 0 1 wr13b rr13b 0 1 1 0 wr14b rr14b (wr7 b) 0 1 1 1 wr15b rr15b 1 0 0 0 wr8a rr8a 1 0 0 1 wr9 rr9a (wr3a) 1 0 1 0 wr10a rr10a 1 0 1 1 wr11a rr11a (wr10a) 1 1 0 0 wr12a rr12a 1 1 0 1 wr13a rr13a 1 1 1 0 wr14a rr14a (wr7a) 1 1 1 1 wr15a rr15a
amd 30 am85c30 table 6. sdlc/hdlc enhancements and 10 19 bit fifo enabled a/ b pnt 2 pnt 1 pnt 0 write read 0 0 0 0 wr0b rr0b 0 0 0 1 wr1b rr1b 0 0 1 0 wr2 rr2b 0 0 1 1 wr3b rr3b 0 1 0 0 wr4b rr4b (wr4b) 0 1 0 1 wr5b rr5b (wr5b) 0 1 1 0 wr6b rr6b 0 1 1 1 wr7b rr7b 1 0 0 0 wr0a rr0a 1 0 0 1 wr1a rr1a 1 0 1 0 wr2 rr2a 1 0 1 1 wr3a rr3a 1 1 0 0 wr4a rr4a (wr4a) 1 1 0 1 wr5a rr5a (wr5a) 1 1 1 0 wr6a rr6a 1 1 1 1 wr7a rr7a with the point high command: a/ b pnt 2 pnt 1 pnt 0 write read 0 0 0 0 wr8b rr8b 0 0 0 1 wr9 rr9 (wr3b) 0 0 1 0 wr10b rr10b 0 0 1 1 wr11b rr11b (wr10b) 0 1 0 0 wr12b rr12b 0 1 0 1 wr13b rr13b 0 1 1 0 wr14b rr14b (wr7 b) 0 1 1 1 wr15b rr15b 1 0 0 0 wr8a rr8a 1 0 0 1 wr9 rr9a (wr3a) 1 0 1 0 wr10a rr10a 1 0 1 1 wr11a rr11a (wr10a) 1 1 0 0 wr12a rr12a 1 1 0 1 wr13a rr13a 1 1 1 0 wr14a rr14a (wr7 a) 1 1 1 1 wr15a rr15a
amd 31 am85c30 auto rts reset on the cmos escc, if bit d 0 of wr15 and bit d 2 of wr7 are set to 1 and the channel is in sdlc mode, the rts pin may be reset early in the tx underrun routine and the rts pin will remain active until the last 0 bit of the closing flag leaves the txd pin as shown in figure 16. note that in order for this to function properly, bits d 3 and d 2 of wr10 must be set to 1 and 0, respectively. crc character reception nmos am8530h on the nmos am8530h, when the end-of-frame flag is detected, the contents of the receive shift register are transferred to the receive data fifo regardless of the number of bits accumulated. because of the 3-bit delay between the receive sync register and receive shift register, the last 2 bits of the crc check character received are never transferred to the receive data fifo. thus, the received crc characters are unavail- able for use. cmos am85c30 on the am85c30, the option of being able to receive the complete crc characters generated by the transmitter is provided when both bit d 0 of wr15 and bit d 5 of wr7 are set to 1. when these 2 bits are set and an end-of- frame flag is detected, the last 2 bits of the crc will be clocked into the receive shift register before its contents are transferred to the receive data fifo. the data-crc boundary and crc character bit formats for each residue code provided are shown in figures 17a through 17d for each character length selected. data being sent data crc crc flag tx underrun/eom rts bit d 1 wr5 rts pin (active low) figure 16. auto rts reset mode 10216f-20
amd 32 am85c30 dddddc 0 c 1 c 2 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 001 residue code 012 101 ddddddc 0 c 1 dc 0 c 1 c 2 c 3 c 4 c 5 c 6 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 100 residue code 012 010 dddddddc 0 ddc 0 c 1 c 2 c 3 c 4 c 5 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 dddddddd dddc 0 c 1 c 2 c 3 c 4 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 110 dddddddd ddddc 0 c 1 c 2 c 3 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 figure 17a. 5 bits/character 10216f-21
amd 33 am85c30 10216f-21 ddddddc 0 c 1 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 010 residue code 012 110 dddddddc 0 dc 0 c 1 c 2 c 3 c 4 c 5 c 6 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 001 residue code 012 101 dddddddd ddc 0 c 1 c 2 c 3 c 4 c 5 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 dddddddd dddc 0 c 1 c 2 c 3 c 4 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 011 dddddddd ddddc 0 c 1 c 2 c 3 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 100 dddddddd dddddc 0 c 1 c 2 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 figure 17b. 6 bits/character
amd 34 am85c30 10216f-21 dddddddc 0 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 111 residue code 012 100 dddddddd dc 0 c 1 c 2 c 3 c 4 c 5 c 6 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 010 residue code 012 110 dddddddd ddc 0 c 1 c 2 c 3 c 4 c 5 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 dddddddd dddc 0 c 1 c 2 c 3 c 4 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 001 dddddddd ddddc 0 c 1 c 2 c 3 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 101 dddddddd dddddc 0 c 1 c 2 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 011 dddddddd ddddddc 0 c 1 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 figure 17c. 7 bits/character
amd 35 am85c30 dddddddd c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 011 residue code 012 111 dddddddd dc 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 000 residue code 012 100 dddddddd ddc 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 dddddddd dddc 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 010 dddddddd ddddc 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 110 dddddddd dddddc 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 001 dddddddd ddddddc 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 residue code 012 101 dddddddd dddddddc 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 (no residue) (2 residue bits) (4 residue bits) (6 residue bits) (7 residue bits) (5 residue bits) (3 residue bits) (1 residue bit) figure 17d. 8 bits/character 10216f-21 (concluded)
amd 36 am85c30 auto flag mode on the nmos am8530h, if the transmitter is actively mark idling and a frame of data is ready to be transmit- ted, the mark/flag idle bit must be set to 0 before data is written to wr8, otherwise the opening flag will not be sent properly. however, care must be exercised in doing this because the mark idle pattern (eight 1 bits) is trans- mitted 8 bits at a time, and all 8 bits must have trans- ferred out of the transmit shift register before a flag may be loaded and sent. if data is written into the trans- mit buffer (wr8) before the flag is loaded into the trans- mit shift register, the data character written to wr8 will supersede flag transmission and the opening flag will not be transmitted. on the cmos am85c30, if bit d 0 of wr15 is set to 1 and the escc is programmed for sdlc operation, an option is provided via bit d 0 of wr7 that eliminates this re- quirement. if bit d 0 of wr7 is set to 1 and a character is written to the transmit buffer while the transmitter is mark idling, the mark/flag idle bit in wr10 need not be reset to 0 in order to have the opening flag sent because the transmitter will automatically send it before com- mencing to send data. in addition, as long as bit d 0 of wr15 and bit d 1 of wr7 are set to 1, the crc transmit generator will be auto- matically preset to the initial state programmed by bit d 7 of wr10 (so the reset tx crc generator command is also not necessary), and the tx underrun/eom latch will be reset automatically on every new frame sent. this ensures that an opening flag and proper crc genera- tion and transmission will always be sent without proc- essor intervention under varying bus latency conditions. auto transmit crc generator preset the nmos am8530h does not automatically preset the crc generator prior to frame transmission. this must be done in software, usually during the initialization rou- tine. this is accomplished by issuing the reset tx crc generator command via wr0. for proper results, this command must be issued while the transmitter is en- abled and idling and before any data are written to the transmit buffer. in addition, if crc is to be used, the transmit crc gen- erator must be enabled by setting bit d 0 of wr5 to 1. crc is normally calculated on all characters between opening and closing flags, so this bit should be set to 1 at initialization and never changed. on the cmos am85c30, setting bit d 0 of wr15 to 1 will cause the transmit crc generator to be preset auto- matically every time an opening flag is sent, so the re- set tx crc generator command is not necessary. auto tx underrun/eom latch reset on the escc, the transmission of the crc check char- acters is controlled by the transmit crc enable bit in wr5 (d 0 ) and the tx underrun/eom bit in rr0 (d 6 ). however, if the transmit enable bit is set to 0 when a transmit underrun (i.e., both the transmit buffer and transmit shift register become empty) occurs, the crc check characters will not be sent regardless of the state of the tx underrun/eom bit. if the transmit enable bit is set to 1 when an underrun occurs, then the state of the tx underrun/eom bit and the abort/flag on underrun bit in wr10 (d 2 ) determine the action taken by the transmitter. the abort/flag on underrun bit may be set or reset by the processor, whereas the tx underrun/eom bit is set by the transmit- ter and can only be reset by the processor via the reset tx underrun/eom command in wr0. if the tx underrun/eom bit is set to 1 when an underrun occurs, the transmitter will close the frame by sending a flag; however, if this bit is set to 0, the frame data will be appended with either the accumulated crc characters followed by a flag or an abort pattern followed by a flag, depending on the state of the abort/flag on underrun bit in the wr10 (d 2 ). in either case, after the closing flag is sent, the transmitter will idle the transmission line as specified by the mark/flag idle bit d 3 in wr10. hence, if the crc check characters are to be properly appended to a frame, the abort/flag on underrun bit must be set to 0, and the reset tx underrun/eom com- mand must be issued after the first but before the last character is written to the transmit buffer. this will en- sure that either an abort or the crc will be transmitted if an underrun occurs. normally, the abort/flag on under- run bit in wr10 should be set to 1 around the same time that the tx underrun/eom bit is reset so that an abort will be sent if the transmitter accidentally underruns, and then set to 0 near the end of the frame to allow the cor- rect transmission of crc. on the am85c30, if bit d 0 of wr15 is set to 1, the option of having the tx underrun/eom bit reset automatically at the start of every frame is provided via bit d 1 of wr7 . this helps alleviate the software burden of having to re- spond within one character time when high-speed data are being sent. sdlc/hdlc nrzi transmitter disabling on the nmos am8530h, if nrzi encoding is being used and the transmitter is disabled, the state of the txd pin will depend on the last bit sent. that is, the txd pin may either idle in a low or high state as shown in figure 18. on the cmos am85c30, an option is provided that al- lows setting the txd pin high when operating in sdlc mode with nrzi encoding enabled. if bit d 0 of wr15 is set to 1, then bit d 3 of wr7 can be used to set the txd pin high. note that the operation of this bit is independ- ent of the tx enable bit in wr5. the tx enable bit in wr5 is used to disable and enable the transmitter,
amd 37 am85c30 transmitter disabled here 110011111100 txd pin output (nrzi encoded) hi lo 10216f-22 figure 18. transmitter disabling with nrzi encoding whereas bit d 3 of wr7 acts as a pseudo transmitter dis- able and enable by just forcing the txd pin high when set even though the transmitter may actually be mark or flag idling. care must be used when setting this bit be- cause any character being transmitted at the time this bit is set will be chopped off, and data written to the trans- mit buffer while this bit is set will be lost. when the transmit underrun occurs and the crc and closing flag have been sent, bit d 3 can be set to pull txd high. when ready to start sending data again this bit must be reset to 0 before the first character is written to the transmit buffer. note that resetting this bit causes the txd pin to take whatever state the nrzi encoder is in at the time, so synchronization at the receiver may take longer because the first transition seen on the txd pin may not coincide with a bit boundary. note that in or- der for this to function properly, bits d 3 and d 2 of wr10 must be set to 1 and 0, respectively. interrupt masking without intack the nmos am8530hs ability to mask lower priority in- terrupts is done via the ius bit. this bit is internal to the scc and is not observable by the processor. being able to automatically mask lower priority interrupts allows a modular approach to coding interrupt routines. how- ever, using the masking capabilities of the nmos scc requires that the intack cycle be generated. in stand- alone applications, having to generate intack through external hardware in order to use this capability is an unnecessary expense. on the cmos am85c30, if bit d 5 in wr9 is set to 1, the intack cycle does not need to be generated in order to have the ius bit set. this allows the user to respond to escc interrupt requests with a software acknowledg- ment through rr2. when bit d 5 in wr9 is set and an interrupt occurs, a read to rr2 emulates a hardware interrupt acknowledge cycle as it functions in vectored mode. in this case the cpu must first read rr2 to deter- mine the internal interrupt source and then jump to the appropriate interrupt routine. reading rr2 sets the ius bit for the highest priority ip. after the interrupting condi- tion is cleared, the routine can then read rr3 to deter- mine if any other ips are set and clear them. at the end of the interrupt routine, a reset ius command must be issued to unlock the internal daisy chain. since the cpu can acknowledge the escc of highest priority with a read of its rr2 interrupt vector, there is no need for an external daisy chain. iei for all escc de- vices should be tied active high. when acknowledging an escc interrupt request, the cpu must issue one read to rr2 per interrupt request. the modified inter- rupt vector can be read from channel b, or the original vector stored in wr2 can be read from channel a. either action will produce the same internal actions on the ius logic. note that the no vector and vector in- cludes status bits in wr9 are ignored when bit d 5 in wr9 is set to 1. 2-mb/s fm data transmission and reception the 16-mhz version of the cmos am85c30 (am85c30-16) is capable of transmitting and receiving fm-encoded data at the rate of 2 mb/s. this is accom- plished by applying a 32-mhz clock to the rtxc pin and assigning this waveform to drive the internal digital phase-locked loop (dpll) clock. this feature allows the user to send both clock and data information over the same line at 2 mb/s and can eliminate external dplls required for high-speed nrz data clock generation.
amd 38 am85c30 absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . voltage at any pin relative to v ss C0.5 to +7.0 v . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a )0 c to +70 c . . . . . . . supply voltage (v cc ) +5 v 10% . . . . . . . . . . . . . industrial (i) devices ambient temperature (t a ) C40 c to +85 c . . . . . supply voltage (v cc )5 v 10% . . . . . . . . . . . . . . military (m) devices case temperature (t c ) C55 c to 125 c . . . . . . . supply voltage (v cc )5 v 10% . . . . . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating range parameter parameter symbol description test conditions min max unit v ih input high voltage commercial 2.2 v cc +0.3* v v il input low voltage C0.3* 0.8 v v oh1 output high voltage i oh = C1.6 ma 2.4 v v oh2 output high voltage i oh = C250 m av cc C0.8 v v ol output low voltage i ol = +2.0 ma 0.4 v i il input leakage 0.4 v v in 2.4 v 10.0 m a i ol output leakage 0.4 v v out 2.4 v 10.0 m a i cc1 v cc supply current 8.192 mhz 18 ma 10 mhz inputs at 18 ma 12 mhz voltage rails, 22 ma 16.384 mhz output unloaded 22 ma c in input capacitance 10 pf c out output capacitance 15 pf c mo bidirectional capacitance 20 pf unmeasured pins returned to ground = 1 mhz over specified temperature range *v ih max and v il min not tested. guaranteed by design. standard test conditions the characteristics below apply for the following stan- dard test conditions, unless otherwise noted. all voltages are referenced to gnd. positive current flows into the referenced pin. standard conditions are as follows: +4.5 v v cc +5.5 v gnd = 0 v 0 c t a 70 c switching test circuits threshold voltage from output under test 75 pf 75 pf 2.2 k +5 v from output under test v t = 1.4 v i oh = 250 m a i ol =2 ma standard test dynamic load circuit open-drain test load 10216f-23 10216f-24
amd 39 am85c30 1 tdpc(req) pclk to w/req valid delay 250 150 80 ns 2 tdpc(w) pclk to wait inactive delay 350 250 180 ns 3 tsrxc(pc) rxc - to pclk - setup time na na na na na na (notes 1, 4 & 8) 4 tsrxd(rxcr) rxd to rxc - setup time 0 0 0 ns (xl mode) (note 1) 5 thrxd(rxcr) rxd to rxc - hold time 150 125 50 ns (xl mode) (note 1) 6 tsrxd(rxcf) rxd to rxc setup time 0 0 0 ns (xl mode) (notes 1, 5) 7 thrxd(rxcf) rxd to rxc hold time 150 125 50 ns (xl mode) (notes 1, 5) 8 tssy(rxc) sync to rxc - setup time C200 C150 C100 ns (note 1) 9 thsy(rxc) sync to rxc - hold time 5tcpc 5tcpc 5tcpc ns (note 1) 10 tstxc(pc) txc to pclk - setup time na na na (notes 2, 4 & 8) 11 tdtxcf(txd) txc to txd delay (xl mode) 200 150 80 ns (note 2) 12 tdtxcr(txd) txc - to txd delay (xl mode) 200 150 80 ns (notes 2, 5) 13 tdtxd(trx) txd to trxc delay 200 140 80 ns (send clock echo) 14a twrtxh rtxc high width (note 6) 150 120 80 ns 14b twrtxh(e) rtxc high width (note 9) 50 40 15.6 ns 15a twrtxi rtxc low width (note 6) 150 120 80 ns 15b twrtxl(e) rtxc low width (note 9) 50 40 15.6 ns 16a tcrtx rtxc cycle time (notes 6, 7) 488 400 244 ns 16b tcrtx(e) rtxc cycle time (note 9) 125 100 31.25 ns 17 tcrtxx crystal oscillator period (note 3) 125 1000 100 1000 62 1000 ns 18 twtrxh trxc high width (note 6) 150 120 80 ns 19 twtrxi trxc low width (note 6) 150 120 80 ns 20 tctrx trxc cycle time (notes 6, 7) 488 400 244 ns 21 twext dcd or cts pulse width 200 120 70 ns 22 twsy sync pulse width 200 120 70 ns switching characteristics over commercial operating range general timing (see figure 19) notes: 1. rxc is rtxc or trxc , whichever is supplying the receive clock. 2. txc is trxc or rtxc, whichever is supplying the transmit clock. 3. both rtxc and sync have 30-pf capacitors to ground connected to them. 4. parameter applies only if the data rate is one-fourth the pclk rate. in all other cases, no phase relationship between rxc and pclk or txc and pclk is required. 5. parameter applies only to fm encoding/decoding. 6. parameter applies only for transmitter and receiver; dpll and baud rate generator timing requirements are identical to chip pclk requirements. 7. the maximum receive or transmit data is 1/4 pclk. 8. external pclk to rxc or txc synchronization requirement eliminated for pclk divide-by-four operation. trxc and rtxc rise and fall times are identical to pclk. reference timing specs tfpc and trpc. tx and rx input clock slow rates should be kept to a maximum of 30 ns. all parameters related to input clk edges should be referenced at the point at which the transition begins or ends, whichever is the worst case. 9. enhanced feature rtxc used as input to internal dpll only. no. parameter symbol parameter description 10 mhz 16.384 mhz min max min max unit 8.192 mhz min max
amd 40 am85c30 switching test input/output waveform 2.4 v 0.4 v test points 2.0 v 0.8 v 2.0 v 0.8 v ac testing: inputs are driven at 2.4 v for a logic 1 and 0.4 v for a logic 0. timing measurements are made at 2.0 v for a logic 1 and 0.8 v for logic 0. 10216f-25 pclk w/req request w/req wait rtxc , trxc receive rxd sync external trxc rtxc transmit txd trxc output rtxc trxc cts , dcd , r1 sync input 11 13 14 15 16 17 18 19 20 21 21 22 22 12 10 8 9 7 6 5 4 3 1 2 10216f-26 figure 19. general timing
amd 41 am85c30 1 tdrxc(req) rxc - w / req valid delay 8 12 tcpc (note 2) 2 tdrxc(w) rxc - to wait inactive delay 8 14 tcpc (notes 1, 2) 3 tdrxc(sy) rxc - to sync valid delay 4 7 tcpc (note 2) 4 tdrxc(int) rxc - to int valid delay 10 16 tcpc (notes 1, 2) 5 tdtxc(req) txc to w / req valid delay 5 8 tcpc (note 3) 6 tdtxc(w) txc to wait inactive delay 5 11 tcpc (notes 1, 3) 7a tdtxc(drq) txc to dtr / req valid delay 4 7 tcpc (note 3) 7b tdtxc(edrq) txc to dtr / req valid delay 5 8 tcpc (notes 3, 4) 8 tdtxc(int) txc to int valid delay 6 10 tcpc (notes 1, 3) 9 tdsy(int) sync transition to int valid 2 6 tcpc delay (note 1) 10 tdext(int) dcd or cts transition to int 2 6 tcpc valid delay (note 1) switching characteristics over commercial operating range (continued) system timing (see figure 20) 1 tdrxc(req) rxc - w / req valid delay 8 12 8 12 tcpc (note 2) 2 tdrxc(w) rxc - to wait inactive delay 8 14 8 14 tcpc (notes 1, 2) 3 tdrxc(sy) rxc - to sync valid delay 4 7 4 7 tcpc (note 2) 4 tdrxc(int) rxc - to int valid delay 10 16 10 16 tcpc (notes 1, 2) 5 tdtxc(req) txc to w / req valid delay 5 8 5 8 tcpc (note 3) 6 tdtxc(w) txc to wait inactive delay 5 11 5 11 tcpc (notes 1, 3) 7a tdtxc(drq) txc to dtr / req valid delay 4 7 4 7 tcpc (note 3) 7b tdtxc(edrq) txc to dtr / req valid delay 5 8 5 8 tcpc (notes 3, 4) 8 tdtxc(int) txc to int valid delay 6 10 6 10 tcpc (notes 1, 3) 9 tdsy(int) sync transition to int valid 2 6 2 6 tcpc delay (note 1) 10 tdext(int) dcd or cts transition to int 2 6 2 6 tcpc valid delay (note 1) notes : 1. open-drain output, measured with open-drain test load. 2. rxc is rtxc or trxc , whichever is supplying the receive clock. 3. txc is trxc or rtxc , whichever is supplying the transmit clock. 4. parameter applies to enhanced request mode only. no. parameter symbol parameter description 8.192 mhz 10 mhz min max min max unit no. parameter symbol parameter description 16.384 mhz min max unit
amd 42 am85c30 switching characteristics over commercial operating range (continued) read and write timing (see figure 21) 1 twpci pclk low width 50 2000 40 2000 26 2000 ns 2 twpch pclk high width 50 2000 40 2000 26 2000 ns 3 tfpc pclk fall time 15 12 8 ns 4 trpc pclk rise time 15 12 8 ns 5 tcpc pclk cycle time 122 4000 100 4000 61 4000 ns 6 tsa(wr) address to wr setup time 70 50 35 ns 7 tha(wr) address to wr - hold time 0 0 0 ns 8 tsa(rd) address to rd setup time 70 50 35 ns 9 tha(rd) address to rd - hold time 0 0 0 ns 10 tsia(pc) i ntack to pclk - setup time 20 20 15 ns 11 tsia(wr) intack to wr setup time 145 120 70 ns (note 1) 12 thia(wr) intack to wr - hold time 0 0 0 ns 13 tsia(rd) intack to rd setup time 145 120 70 ns (note 1) 14 thiai(rd) intack to rd - hold time 0 0 0 ns 15 thia(pc) intack to pclk - hold time 40 30 15 ns 16 tscei(wr) ce low to wr setup time 0 0 0 ns 17 thce(wr) ce to wr - hold time 0 0 0 ns 18 tsceh(wr) ce high to wr setup time 60 50 30 ns 19 tscei(rd) ce low to rd setup time 0 0 0 ns (note 1) 20 thce(rd) ce to rd - hold time (note1) 0 0 0 ns 21 tsceh(rd) ce high to rd setup time 60 50 30 ns (note 1) 22 twrdi rd low width (note 1) 150 125 75 ns 23 tdrd(dra) rd to read data active delay 0 0 0 ns 24 tdrdr(dr) rd - to read data not valid delay 0 0 0 ns 25 tdrdf(dr) rd to read data valid delay 140 120 70 ns 26 tdrd(drz) rd - to read data float delay 40 35 20 ns (note 2) notes: 1. parameter does not apply to interrupt acknowledge transactions. 2. float delay is defined as the time at which the data bus is released from its drive state with a maximum dc load and minimum ac load. no. parameter symbol parameter description 10 mhz 16.384 mhz min max min max unit 8.192 mhz min max
amd 43 am85c30 2 9 8 7 3 5 rtxc trxc receive w / req request w / req wait sync output int rtxc trxc transmit w / req request w / req wait dtr req request int cts , dcd , ri sync input int 10 6 4 1 10216f-27 figure 20. system timing
amd 44 am85c30 pclk a/ b , d/ c intack ce rd d 7 Cd 0 read wr d 7 Cd 0 write w / req wait dtr / req request w / req request int 12 6 3 4 11 8 10 13 15 7 19 16 23 29 10 24 21 31 32 35 33 34 37 36 14 1 2 5 9 18 20 22 17 25 27 26 28 30 valid valid 10216f-28 figure 21. read and write timing
amd 45 am85c30 switching characteristics over commercial operating range (continued) interrupt acknowledge timing, reset timing, cycle timing (see figures 22C24) 27 tda(dr) address required valid to read 220 160 100 ns data valid delay 28 twwri wr low width 150 125 75 ns 29 tdwrf(dw) wr to write data valid 35 35 20 ns 30 thdw(wr) write data to wr - hold time 0 0 0 ns 31 tdwr(w) wr to wait valid delay (note 2) 170 100 50 ns 32 tdrd(w) rd to wait valid delay (note 2) 170 100 50 ns 33 tdwrf(req) wr to w / req not valid delay 170 120 70 ns 34 tdrdf(req) rd to w / req not valid delay 170 120 70 ns 35a tdwrr(req) wr to dtr / req not valid delay 4.0tcpc 4.0tcpc 4.0tcpc ns 35b tdwrr(ereq) wr to dtr / req not valid delay 120 120 70 ns 36 tdrdr(req) rd - to dtr / req not valid delay na na na ns 37 tdpc(int) pclk to int valid delay (note 2) 500 400 175 ns 38 tdiai(rd) intack to rd (acknowledge) 150 125 50 ns delay (note 3) 39 twrda rd (acknowledge) width 150 125 75 ns 40 tdrda(dr) rd (acknowledge) to read 140 120 70 ns data valid delay 41 tsiei(rda) iei to rd (acknowledge) setup 95 80 50 ns time 42 thiei(rda) iei to rd - (acknowledge) hold 0 0 0 ns time 43 tdiei(ieo) iei to ieo delay time 95 80 45 ns 44 tdpc(ieo) pclk - to ieo delay 200 175 80 ns 45 tdrda(int) rd to int inactive delay (note 2) 450 320 200 ns 46 tdrd(wrq) rd - to wr delay for no reset 15 15 10 ns 47 tdwrq(rd) wr - to rd delay for no reset 15 15 10 ns 48 twres wr and rd coincident low for 150 100 75 ns reset 49 trc valid access recovery time 3.5 3.5 3.5 tcpc (note 1) notes: 1. parameter applies only between transactions involving the escc, if wr/rd falling edge is synchronized to pclk falling edge, then trc = 3tcpc. 2. open-drain output, measured with open-drain test load. 3. parameter is system dependent. for any scc in the daisy chain, tdiai(rd) must be greater than the sum of ddpc(ieo) for the highest priority device in the daisy chain, tsiei(rda) for the scc, and tdiei(ieo) for each device separating them in the daisy chain. 4. parameter applies to enhanced request mode only. no. parameter symbol parameter description 10 mhz 16.384 mhz min max min max unit 8.192 mhz min max
amd 46 am85c30 wr rd 46 47 48 10216f-29 figure 22. reset timing rd or wr ce 49 10216f-30 figure 23. cycle timing pclk intack rd d 7 Cd 0 int iei ieo 10 15 14 38 10 39 24 26 40 42 41 43 44 45 23 valid 10216f-31 figure 24. interrupt acknowledge timing
amd 47 am85c30 1 tdpc(req) pclk to w/req valid delay 250 150 80 ns 2 tdpc(w) pclk to wait inactive delay 350 250 180 ns 3 tsrxc(pc) rxc - to pclk - setup time na na na na na na (notes 1, 4 & 8) 4 tsrxd(rxcr) rxd to rxc - setup time 0 0 0 ns (xl mode) (note 1) 5 thrxd(rxcr) rxd to rxc - hold time 150 125 50 ns (xl mode) (note 1) 6 tsrxd(rxcf) rxd to rxc setup time 0 0 0 ns (xl mode) (notes 1, 5) 7 thrxd(rxcf) rxd to rxc hold time 150 125 50 ns (xl mode) (notes 1, 5) 8 tssy(rxc) sync to rxc - setup time C200 C150 C100 ns (note 1) 9 thsy(rxc) sync to rxc - hold time 5tcpc 5tcpc 5tcpc ns (note 1) 10 tstxc(pc) txc to pclk - setup time na na na (notes 2, 4 & 8) 11 tdtxcf(txd) txc to txd delay (xl mode) 200 150 80 ns (note 2) 12 tdtxcr(txd) txc - to txd delay (xl mode) 200 150 80 ns (notes 2, 5) 13 tdtxd(trx) txd to trxc delay 200 140 80 ns (send clock echo) 14a twrtxh rtxc high width (note 6) 150 120 80 ns 14b twrtxh(e) rtxc high width (note 9) 50 40 15.6 ns 15a twrtxi rtxc low width (note 6) 150 120 80 ns 15b twrtxl(e) rtxc low width (note 9) 50 40 15.6 ns 16a tcrtx rtxc cycle time (notes 6, 7) 488 400 244 ns 16b tcrtx(e) rtxc cycle time (note 9) 125 100 31.25 ns 17 tcrtxx crystal oscillator period (note 3) 125 1000 100 1000 62 1000 ns 18 twtrxh trxc high width (note 6) 150 120 80 ns 19 twtrxi trxc low width (note 6) 150 120 80 ns 20 tctrx trxc cycle time (notes 6, 7) 488 400 244 ns 21 twext dcd or cts pulse width 200 120 70 ns 22 twsy sync pulse width 200 120 70 ns switching characteristics over military/industrial operating range general timing (see figure 19) notes: 1. rxc is rtxc or trxc , whichever is supplying the receive clock. 2. txc is trxc or rtxc, whichever is supplying the transmit clock. 3. both rtxc and sync have 30-pf capacitors to ground connected to them. 4. parameter applies only if the data rate is one-fourth the pclk rate. in all other cases, no phase relationship between rxc and pclk or txc and pclk is required. 5. parameter applies only to fm encoding/decoding. 6. parameter applies only for transmitter and receiver; dpll and baud rate generator timing requirements are identical to chip pclk requirements. 7. the maximum receive or transmit data is 1/4 pclk. 8. external pclk to rxc or txc synchronization requirement eliminated for pclk divide-by-four operation. trxc and rtxc rise and fall times are identical to pclk. reference timing specs tfpc and trpc. tx and rx input clock slow rates should be kept to a maximum of 30 ns. all parameters related to input clk edges should be referenced at the point at which the transition begins or ends, whichever is the worst case. 9. enhanced feature rtxc used as input to internal dpll only. no. parameter symbol parameter description 10 mhz 16.384 mhz min max min max unit 8.192 mhz min max
amd 48 am85c30 1 tdrxc(req) rxc - w / req valid delay 8 12 tcpc (note 2) 2 tdrxc(w) rxc - to wait inactive delay 8 14 tcpc (notes 1, 2) 3 tdrxc(sy) rxc - to sync valid delay 4 7 tcpc (note 2) 4 tdrxc(int) rxc - to int valid delay 10 16 tcpc (notes 1, 2) 5 tdtxc(req) txc to w / req valid delay 5 8 tcpc (note 3) 6 tdtxc(w) txc to wait inactive delay 5 11 tcpc (notes 1, 3) 7a tdtxc(drq) txc to dtr / req valid delay 4 7 tcpc (note 3) 7b tdtxc(edrq) txc to dtr / req valid delay 5 8 tcpc (notes 3, 4) 8 tdtxc(int) txc to int valid delay 6 10 tcpc (notes 1, 3) 9 tdsy(int) sync transition to int valid 2 6 tcpc delay (note 1) 10 tdext(int) dcd or cts transition to int 2 6 tcpc valid delay (note 1) 1 tdrxc(req) rxc - w / req valid delay 8 12 8 12 tcpc (note 2) 2 tdrxc(w) rxc - to wait inactive delay 8 14 8 14 tcpc (notes 1, 2) 3 tdrxc(sy) rxc - to sync valid delay 4 7 4 7 tcpc (note 2) 4 tdrxc(int) rxc - to int valid delay 10 16 10 16 tcpc (notes 1, 2) 5 tdtxc(req) txc to w / req valid delay 5 8 5 8 tcpc (note 3) 6 tdtxc(w) txc to wait inactive delay 5 11 5 11 tcpc (notes 1, 3) 7a tdtxc(drq) txc to dtr / req valid delay 4 7 4 7 tcpc (note 3) 7b tdtxc(edrq) txc to dtr / req valid delay 5 8 5 8 tcpc (notes 3, 4) 8 tdtxc(int) txc to int valid delay 6 10 6 10 tcpc (notes 1, 3) 9 tdsy(int) sync transition to int valid 2 6 2 6 tcpc delay (note 1) 10 tdext(int) dcd or cts transition to int 2 6 2 6 tcpc valid delay (note 1) notes : 1. open-drain output, measured with open-drain test load. 2. rxc is rtxc or trxc , whichever is supplying the receive clock. 3. txc is trxc or rtxc , whichever is supplying the transmit clock. 4. parameter applies to enhanced request mode only. no. parameter symbol parameter description 8.192 mhz 10 mhz min max min max unit no. parameter symbol parameter description 16.384 mhz min max unit switching characteristics over military/industrial operating range (continued) system timing (see figure 20)
amd 49 am85c30 1 twpci pclk low width 50 1000 40 1000 26 1000 ns 2 twpch pclk high width 50 1000 40 1000 26 1000 ns 3 tfpc pclk fall time 15 12 8 ns 4 trpc pclk rise time 15 12 8 ns 5 tcpc pclk cycle time 122 2000 100 2000 61 2000 ns 6 tsa(wr) address to wr setup time 70 50 35 ns 7 tha(wr) address to wr - hold time 0 0 0 ns 8 tsa(rd) address to rd setup time 70 50 35 ns 9 tha(rd) address to rd - hold time 0 0 0 ns 10 tsia(pc) i ntack to pclk - setup time 20 20 15 ns 11 tsia(wr) intack to wr setup time 145 120 70 ns (note 1) 12 thia(wr) intack to wr - hold time 0 0 0 ns 13 tsia(rd) intack to rd setup time 145 120 70 ns (note 1) 14 thiai(rd) intack to rd - hold time 0 0 0 ns 15 thia(pc) intack to pclk - hold time 40 30 15 ns 16 tscei(wr) ce low to wr setup time 0 0 0 ns 17 thce(wr) ce to wr - hold time 0 0 0 ns 18 tsceh(wr) ce high to wr setup time 60 50 30 ns 19 tscei(rd) ce low to rd setup time 0 0 0 ns (note 1) 20 thce(rd) ce to rd - hold time (note1) 0 0 0 ns 21 tsceh(rd) ce high to rd setup time 60 50 30 ns (note 1) 22 twrdi rd low width (note 1) 150 125 75 ns 23 tdrd(dra) rd to read data active delay 0 0 0 ns 24 tdrdr(dr) rd - to read data not valid delay 0 0 0 ns 25 tdrdf(dr) rd to read data valid delay 140 125 70 ns 26 tdrd(drz) rd - to read data float delay 40 35 20 ns (note 2) notes: 1. parameter does not apply to interrupt acknowledge transactions. 2. float delay is defined as the time at which the data bus is released from its drive state with a maximum dc load and minimum ac load. no. parameter symbol parameter description 10 mhz 16.384 mhz min max min max unit 8.192 mhz min max switching characteristics over military/industrial operating range (continued) read and write timing (see figure 21)
amd 50 am85c30 27 tda(dr) address required valid to read 220 160 100 ns data valid delay 28 twwri wr low width 150 125 75 ns 29 tdwrf(dw) wr to write data valid 35 35 20 ns 30 thdw(wr) write data to wr - hold time 0 0 0 ns 31 tdwr(w) wr to wait valid delay (note 2) 170 100 50 ns 32 tdrd(w) rd to wait valid delay (note 2) 170 100 50 ns 33 tdwrf(req) wr to w / req not valid delay 170 120 70 ns 34 tdrdf(req) rd to w / req not valid delay 170 120 70 ns 35a tdwrr(req) wr to dtr / req not valid delay 4.0tcpc 4.0tcpc 4.0tcpc ns 35b tdwrr(ereq) wr to dtr / req not valid delay 120 120 70 ns 36 tdrdr(req) rd - to dtr / req not valid delay na na na ns 37 tdpc(int) pclk to int valid delay (note 2) 500 400 175 ns 38 tdiai(rd) intack to rd (acknowledge) 150 125 50 ns delay (note 3) 39 twrda rd (acknowledge) width 150 125 75 ns 40 tdrda(dr) rd (acknowledge) to read 140 120 70 ns data valid delay 41 tsiei(rda) iei to rd (acknowledge) setup 95 80 50 ns time 42 thiei(rda) iei to rd - (acknowledge) hold 0 0 0 ns time 43 tdiei(ieo) iei to ieo delay time 95 80 45 ns 44 tdpc(ieo) pclk - to ieo delay 200 175 80 ns 45 tdrda(int) rd to int inactive delay (note 2) 450 320 200 ns 46 tdrd(wrq) rd - to wr delay for no reset 15 15 10 ns 47 tdwrq(rd) wr - to rd delay for no reset 15 15 10 ns 48 twres wr and rd coincident low for 150 100 75 ns reset 49 trc valid access recovery time 3.5 3.5 3.5 tcpc (note 1) notes: 1 parameter applies only between transactions involving the escc, if wr/rd falling edge is synchronized to pclk falling edge, then trc = 3tcpc. 2. open-drain output, measured with open-drain test load. 3. parameter is system dependent. for any scc in the daisy chain, tdiai(rd) must be greater than the sum of ddpc(ieo) for the highest priority device in the daisy chain, tsiei(rda) for the scc, and tdiei(ieo) for each device separating them in the daisy chain. 4. parameter applies to enhanced request mode only. no. parameter symbol parameter description 10 mhz 16.384 mhz min max min max unit 8.192 mhz min max switching characteristics over military/industrial operating range (continued) interrupt acknowledge timing, reset timing, cycle timing (see figures 22C24)
amd 51 am85c30 physical dimensions* cd 040 .050 .065 .005 min .100 bsc .160 .220 .015 .022 .015 .060 2.035 2.080 .565 .605 06824d bz13 cd 040 5/20/92 c dc .125 .160 .008 .012 .590 .615 0? 15 .700 max end view side view top view 1 .098 max .150 min *for reference only. bsc is an ansi standard for basic space centering.
amd 52 am85c30 physical dimensions cl 044 .064 .100 .054 .088 plane 2 plane 1 .500 bsc .050 bsc .045 .055 .006 .022 .003 .015 .015 min index corner .020 x 45 ref. (optional) 06825e aw 29 8/15/91 c dc .500 bsc .040 x 45 ref. (3x) (optional) .250 bsc .625 bsc .640 .660 .625 bsc .640 .660 .250 bsc .022 .028
amd 53 am85c30 physical dimensions pd 040 06823e cj76 pd 040 1/21/93 c dc .045 .065 .005 min .090 .110 .140 .225 .014 .022 .015 .060 2.040 2.080 1 .530 .580 .120 .160 .008 .015 .600 .625 0 7 .630 .700 end view side view top view pl 044 .050 ref .042 .048 .650 .656 .685 .695 .650 .656 .685 .695 .042 .056 .165 .180 .090 .120 .009 .015 .500 ref .013 .021 .590 .630 .020 min .025 .045 06752f cj48 pl 044 1/21/93 c dc r .026 .032 top view side view trademarks copyright ? 1993 advanced micro devices, inc. all rights reserved. amd is a registered trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
publication# 10216 rev. f amendment /1 issue date: december 1993 advanced micro devices am85c30 enhanced serial communications controller amendment summary this amendment adds information to the final data sheet on the commercial and industrial 20 mhz speed grades. this latest offering complements the 8, 10, and 16 mhz speed grades currently offered by amd. a few minor inaccuracies are also corrected and a clari- fication section on hardware reset in software that had been previously available as a separate page is now re- printed here for ease of reference. details page 1: distinctive characteristics n add 20 mhz/5.0 mbyte/s under fastest data rate of any am85c30 bullet. page 4: ordering information, commodity products n change word from commodity to standard n add am85c30-20 to valid combinations and -20 = 20 mhz to speed option page 5: ordering information, industrial products n add am85c30-20 to valid combinations and -20 = 20 mhz to speed option n change package description from j = 44-pin leadless chip carrier (pl 044) to j = 44-pin plastic leaded chip carrier (pl 044) . page 38: dc characteristics n delete i cc1 for the 12 mhz speed grade since this speed is not offered. n add i cc1 for the 20 mhz speed grade now being offered. n change symbol from c mo to c i/o and add note on capacitance. pages 39 and 47: switching characteristics n in note 8 change from clock slow rates to clock slew rates . pages 39C50: switching characteristics n add minimum and maximum limits, where appro- priate, for the 20 mhz speed grade now being offered. note: minor corrections should be made on the exist- ing data sheets. however, for ease of use, pages 38C50 as well as the page on hardware reset in soft- ware are printed with this amendment.
a m e n d m e n t amd 2 am85c30 absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . voltage at any pin relative to v ss C0.5 to +7.0 v . . . . . . . . . . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a )0 c to +70 c . . . . . . . . . . supply voltage (v cc ) +5 v 10% . . . . . . . . . . . . . . . . industrial (i) devices ambient temperature (t a ) C40 c to +85 c . . . . . . . . supply voltage (v cc )5 v 10% . . . . . . . . . . . . . . . . . military (m) devices case temperature (t c ) C55 c to +125 c . . . . . . . . . supply voltage (v cc )5 v 10% . . . . . . . . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over operating range unless otherwise specified parameter parameter symbol description test conditions min max unit v ih input high voltage 2.2 v cc +0.3* v v il input low voltage C0.3* 0.8 v v oh1 output high voltage i oh = C1.6 ma 2.4 v v oh2 output high voltage i oh = C250 m a v cc C0.8 v v ol output low voltage i ol = +2.0 ma 0.4 v i il input leakage 0.4 v v in 2.4 v 10.0 m a i ol output leakage 0.4 v v out 2.4 v 10.0 m a i cc1 v cc supply current 8.192 mhz 18 ma 10 mhz 18 ma 16.384 mhz 22 ma 20 mhz 22 ma c in ** input capacitance 10 pf c out ** output capacitance 15 pf c i/o ** bidirectional capacitance 20 pf *v ih max and v il min not tested. guaranteed by design. **these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. unmeasured pins returned to ground = 1 mhz over specified temperature range inputs at voltage rails, output unloaded standard test conditions the characteristics below apply for the following stan- dard test conditions, unless otherwise noted. all voltages are referenced to gnd. positive current flows into the referenced pin. standard conditions are as follows: +4.5 v v cc +5.5 v gnd = 0 v 0 c t a 70 c switching test circuits threshold voltage from output under test 75 pf 75 pf 2.2k +5 v from output under test v t = 1.4 v i oh = 250 m a i ol =2 ma standard test dynamic load circuit open-drain test load 10216f/1-1 10216f/1-2
a m e n d m e n t amd 3 am85c30 1 tdpc(req) pclk to w/req valid delay 250 150 80 70 ns 2 tdpc(w) pclk to wait inactive delay 350 250 180 170 ns 3 tsrxc(pc) rxc - to pclk - setup time na na na na na na na na ns (notes 1, 4 & 8) 4 tsrxd(rxcr) rxd to rxc - setup time 0000ns (xl mode) (note 1) 5 thrxd(rxcr) rxd to rxc - hold time 150 125 50 45 ns (xl mode) (note 1) 6 tsrxd(rxcf) rxd to rxc setup time 0000ns (xl mode) (notes 1, 5) 7 thrxd(rxcf) rxd to rxc hold time 150 125 50 45 ns (xl mode) (notes 1, 5) 8 tssy(rxc) sync to rxc - setup time C200 C150 C100 C90 ns (note 1) 9 thsy(rxc) sync to rxc - hold time 5tcpc 5tcpc 5tcpc 5tcpc ns (note 1) 10 tstxc(pc) txc to pclk - setup time na na na na (notes 2, 4 & 8) 11 tdtxcf(txd) txc to txd delay (xl mode) 200 150 80 70 ns (note 2) 12 tdtxcr(txd) txc - to txd delay (xl mode) 200 150 80 70 ns (notes 2, 5) 13 tdtxd(trx) txd to trxc delay 200 140 80 70 ns (send clock echo) 14a twrtxh rtxc high width (note 6) 150 120 80 70 ns 14b twrtxh(e) rtxc high width (note 9) 50 40 15.6 15.6 ns 15a twrtxi rtxc low width (note 6) 150 120 80 70 ns 15b twrtxl(e) rtxc low width (note 9) 50 40 15.6 15.6 ns 16a tcrtx rtxc cycle time (notes 6, 7) 488 400 244 200 ns 16b tcrtx(e) rtxc cycle time (note 9) 125 100 31.25 31.25 ns 17 tcrtxx crystal oscillator period (note 3) 125 1000 100 1000 62 1000 61 1000 ns 18 twtrxh trxc high width (note 6) 150 120 80 70 ns 19 twtrxi trxc low width (note 6) 150 120 80 70 ns 20 tctrx trxc cycle time (notes 6, 7) 488 400 244 200 ns 21 twext dcd or cts pulse width 200 120 70 60 ns 22 twsy sync pulse width 200 120 70 60 ns switching characteristics over commercial operating range unless otherwise specifiedgeneral timing (see figure 19) notes : 1 . rxc is rtxc or trxc , whichever is supplying the receive clock. 2. txc is trxc or rtxc, whichever is supplying the transmit clock. 3. both rtxc and sync have 30-pf capacitors to ground connected to them. 4. parameter applies only if the data rate is one-fourth the pclk rate. in all other cases, no phase relationship between rxc and pclk or txc and pclk is required. 5. parameter applies only to fm encoding/decoding. 6. parameter applies only for transmitter and receiver; dpll and baud rate generator timing requirements are identical to chip pclk requirements. 7. the maximum receive or transmit data is 1/4 pclk. 8. external pclk to rxc or txc synchronization requirement eliminated for pclk divide-by-four operation. trxc and rtxc rise and fall times are identical to pclk. reference timing specs tfpc and trpc. tx and rx input clock slew rates should be kept to a maximum of 30 ns. all parameters related to input clk edges should be referenced at the point at which the transition begins or ends, whichever is the worst case. 9. enhanced feature rtxc used as input to internal dpll only. no. parameter symbol parameter description 10 mhz 20 mhz min max min max unit 8.192 mhz min max min max 16.384 mhz
a m e n d m e n t amd 4 am85c30 switching test input/output waveform 2.4 v 0.4 v test points 2.0 v 0.8 v 2.0 v 0.8 v ac testing: inputs are driven at 2.4 v for a logic 1 and 0.4 v for a logic 0. timing measurements are made at 2.0 v for a logic 1 and 0.8 v for logic 0. 10216f/1-3 pclk w/req request w/req wait rtxc , trxc receive rxd sync external trxc rtxc transmit txd trxc output rtxc trxc cts, dcd, r1 sync input 11 13 14 15 16 17 18 19 20 21 21 22 22 12 10 8 9 7 6 5 4 3 1 2 10216f/1-4 figure 19. general timing
a m e n d m e n t amd 5 am85c30 1 tdrxc(req) rxc - w / req valid delay 8 12 8 12 tcpc (note 2) 2 tdrxc(w) rxc - to wait inactive delay 8 14 8 14 tcpc (notes 1, 2) 3 tdrxc(sy) rxc - to sync valid delay 4 7 4 7 tcpc (note 2) 4 tdrxc(int) rxc - to int valid delay 10 16 10 16 tcpc (notes 1, 2) 5 tdtxc(req) txc to w / req valid delay 5 8 5 8 tcpc (note 3) 6 tdtxc(w) txc to wait inactive delay 5 11 5 11 tcpc (notes 1, 3) 7a tdtxc(drq) txc to dtr / req valid delay 4 7 4 7 tcpc (note 3) 7b tdtxc(edrq) txc to dtr / req valid delay 5 8 5 8 tcpc (notes 3, 4) 8 tdtxc(int) txc to int valid delay 6 10 6 10 tcpc (notes 1, 3) 9 tdsy(int) sync transition to int valid 2 6 2 6 tcpc delay (note 1) 10 tdext(int) dcd or cts transition to int 2 6 2 6 tcpc valid delay (note 1) switching characteristics over commercial operating range (continued) system timing (see figure 20) 1 tdrxc(req) rxc - w / req valid delay 8 12 8 12 tcpc (note 2) 2 tdrxc(w) rxc - to wait inactive delay 8 14 8 14 tcpc (notes 1, 2) 3 tdrxc(sy) rxc - to sync valid delay 4 7 4 7 tcpc (note 2) 4 tdrxc(int) rxc - to int valid delay 10 16 10 16 tcpc (notes 1, 2) 5 tdtxc(req) txc - to w / req valid delay 5 8 5 8 tcpc (note 3) 6 tdtxc(w) txc to wait inactive delay 5 11 5 11 tcpc (notes 1, 3) 7a tdtxc(drq) txc to dtr / req valid delay 4 7 4 7 tcpc (note 3) 7b tdtxc(edrq) txc to dtr / req valid delay 5 8 5 8 tcpc (notes 3, 4) 8 tdtxc(int) txc to int valid delay 6 10 6 10 tcpc (notes 1, 3) 9 tdsy(int) sync transition to int valid 2 6 2 6 tcpc delay (note 1) 10 tdext(int) dcd or cts transition to int 2 6 2 6 tcpc valid delay (note 1) notes : 1. open-drain output, measured with open-drain test load. 2. rxc is rtxc or trxc , whichever is supplying the receive clock. 3. txc is trxc or rtxc , whichever is supplying the transmit clock. 4. parameter applies to enhanced request mode only. no. parameter symbol parameter description 8.192 mhz 10 mhz min max min max unit no. parameter symbol parameter description 16.384 mhz min max unit min max 20 mhz
a m e n d m e n t amd 6 am85c30 switching characteristics over commercial operating range (continued) read and write timing (see figure 21) 1 twpci pclk low width 50 2000 40 2000 26 2000 22 2000 ns 2 twpch pclk high width 50 2000 40 2000 26 2000 22 2000 ns 3 tfpc pclk fall time 15 12 8 5 ns 4 trpc pclk rise time 15 12 8 5 ns 5 tcpc pclk cycle time 122 4000 100 4000 61 4000 50 2000 ns 6 tsa(wr) address to wr setup time 70 50 35 30 ns 7 tha(wr) address to wr - hold time 0000ns 8 tsa(rd) address to rd setup time 70 50 35 30 ns 9 tha(rd) address to rd - hold time 0000ns 10 tsia(pc) i ntack to pclk - setup time 20 20 15 15 ns 11 tsia(wr) intack to wr setup time 145 120 70 65 ns (note 1) 12 thia(wr) intack to wr - hold time 0000ns 13 tsia(rd) intack to rd setup time 145 120 70 65 ns (note 1) 14 thiai(rd) intack to rd - hold time 0000ns 15 thia(pc) intack to pclk - hold time 40 30 15 15 ns 16 tscei(wr) ce low to wr setup time 0000ns 17 thce(wr) ce to wr - hold time 0000ns 18 tsceh(wr) ce high to wr setup time 60 50 30 25 ns 19 tscei(rd) ce low to rd setup time 0000ns (note 1) 20 thce(rd) ce to rd - hold time (note1) 0000ns 21 tsceh(rd) ce high to rd setup time 60 50 30 25 ns (note 1) 22 twrdi rd low width (note 1) 150 125 75 65 ns 23 tdrd(dra) rd to read data active delay 0000ns 24 tdrdr(dr) rd - to read data not valid delay 0000ns 25 tdrdf(dr) rd to read data valid delay 140 120 70 65 ns 26 tdrd(drz) rd - to read data float delay 40 35 20 20 ns (note 2) notes: 1. parameter does not apply to interrupt acknowledge transactions. 2. float delay is defined as the time at which the data bus is released from its drive state with a maximum dc load and minimum ac load. no. parameter symbol parameter description 10 mhz 20 mhz min max min max unit 8.192 mhz min max min max 16.384 mhz
a m e n d m e n t amd 7 am85c30 2 9 8 7 3 5 rtxc trxc receive w / req request w / req wait sync output int rtxc trxc transmit w / req request w / req wait dtr req request int cts, dcd, ri sync input int 10 6 4 1 10216f/1-5 figure 20. system timing
a m e n d m e n t amd 8 am85c30 pclk a/ b , d/ c intack ce rd d0Cd7 read wr d0Cd7 write w / req wait dtr / req request w / req request int 12 6 3 4 11 8 10 13 15 7 19 16 23 29 10 24 21 31 32 35 33 34 37 36 14 1 2 5 9 18 20 22 17 25 27 26 28 30 valid valid 10216f/1-6 figure 21. read and write timing
a m e n d m e n t amd 9 am85c30 switching characteristics over commercial operating range (continued) interrupt acknowledge timing, reset timing, cycle timing (see figures 22C24) 27 tda(dr) address required valid to read 220 160 100 90 ns data valid delay 28 twwri wr low width 150 125 75 65 ns 29 tdwrf(dw) wr to write data valid 35 35 20 20 ns 30 thdw(wr) write data to wr - hold time 0000ns 31 tdwr(w) wr to wait valid delay (note 2) 170 100 50 50 ns 32 tdrd(w) rd to wait valid delay (note 2) 170 100 50 50 ns 33 tdwrf(req) wr to w / req not valid delay 170 120 70 65 ns 34 tdrdf(req) rd to w / req not valid delay 170 120 70 65 ns 35a tdwrr(req) wr to dtr / req not valid delay 4tcpc 4tcpc 4tcpc 4tcpc ns 35b tdwrr(ereq) wr to dtr / req not valid delay 120 120 70 65 ns 36 tdrdr(req) rd - to dtr / req not valid delay na na na na ns 37 tdpc(int) pclk to int valid delay (note 2) 500 400 175 160 ns 38 tdiai(rd) intack to rd (acknowledge) 150 125 50 45 ns delay (note 3) 39 twrda rd (acknowledge) width 150 125 75 65 ns 40 tdrda(dr) rd (acknowledge) to read 140 120 70 60 ns data valid delay 41 tsiei(rda) iei to rd (acknowledge) setup 95 80 50 45 ns time 42 thiei(rda) iei to rd - (acknowledge) hold 0000ns time 43 tdiei(ieo) iei to ieo delay time 95 80 45 40 ns 44 tdpc(ieo) pclk - to ieo delay 200 175 80 70 ns 45 tdrda(int) rd to int inactive delay (note 2) 450 320 200 180 ns 46 tdrd(wrq) rd - to wr delay for no reset 15 15 10 10 ns 47 tdwrq(rd) wr - to rd delay for no reset 15 15 10 10 ns 48 twres wr and rd coincident low for 150 100 75 65 ns reset 49 trc valid access recovery time 3.5 3.5 3.5 3.5 (note 1) notes: 1 parameter applies only between transactions involving the escc, if wr/rd falling edge is synchronized to pclk falling edge, then trc = 3tcpc. 2. open-drain output, measured with open-drain test load. 3. parameter is system dependent. for any scc in the daisy chain, tdiai(rd) must be greater than the sum of ddpc(ieo) for the highest priority device in the daisy chain, tsiei(rda) for the scc, and tdiei(ieo) for each device separating them in the daisy chain. 4. parameter applies to enhanced request mode only. no. parameter symbol parameter description 10 mhz 20 mhz min max min max unit 8.192 mhz min max min max 16.384 mhz tcpc
a m e n d m e n t amd 10 am85c30 wr rd 46 47 48 10216f/1-7 figure 22. reset timing rd or wr ce 49 10216f/1-8 figure 23. cycle timing pclk intack rd d0Cd7 int iei ieo 10 15 14 38 10 39 24 26 40 42 41 43 44 45 23 valid 10216f/1-9 figure 24. interrupt acknowledge timing
a m e n d m e n t amd 11 am85c30 1 tdpc(req) pclk to w/req valid delay 250 150 80 70 ns 2 tdpc(w) pclk to wait inactive delay 350 250 180 170 ns 3 tsrxc(pc) rxc - to pclk - setup time na na na na na na na na ns (notes 1, 4 & 8) 4 tsrxd(rxcr) rxd to rxc - setup time 0000ns (xl mode) (note 1) 5 thrxd(rxcr) rxd to rxc - hold time 150 125 50 45 ns (xl mode) (note 1) 6 tsrxd(rxcf) rxd to rxc setup time 0000ns (xl mode) (notes 1, 5) 7 thrxd(rxcf) rxd to rxc hold time 150 125 50 45 ns (xl mode) (notes 1, 5) 8 tssy(rxc) sync to rxc - setup time C200 C150 C100 C90 ns (note 1) 9 thsy(rxc) sync to rxc - hold time 5tcpc 5tcpc 5tcpc 5tcpc ns (note 1) 10 tstxc(pc) txc to pclk - setup time na na na na (notes 2, 4 & 8) 11 tdtxcf(txd) txc to txd delay (xl mode) 200 150 80 70 ns (note 2) 12 tdtxcr(txd) txc - to txd delay (xl mode) 200 150 80 70 ns (notes 2, 5) 13 tdtxd(trx) txd to trxc delay 200 140 80 70 ns (send clock echo) 14a twrtxh rtxc high width (note 6) 150 120 80 70 ns 14b twrtxh(e) rtxc high width (note 9) 50 40 15.6 15.6 ns 15a twrtxi rtxc low width (note 6) 150 120 80 70 ns 15b twrtxl(e) rtxc low width (note 9) 50 40 15.6 15.6 ns 16a tcrtx rtxc cycle time (notes 6, 7) 488 400 244 200 ns 16b tcrtx(e) rtxc cycle time (note 9) 125 100 31.25 31.25 ns 17 tcrtxx crystal oscillator period (note 3) 125 1000 100 1000 62 1000 61 1000 ns 18 twtrxh trxc high width (note 6) 150 120 80 70 ns 19 twtrxi trxc low width (note 6) 150 120 80 70 ns 20 tctrx trxc cycle time (notes 6, 7) 488 400 244 200 ns 21 twext dcd or cts pulse width 200 120 70 60 ns 22 twsy sync pulse width 200 120 70 60 ns switching characteristics over military/industrial operating range unless otherwise specifiedgeneral timing (see figure 19) notes : 1 . rxc is rtxc or trxc , whichever is supplying the receive clock. 2. txc is trxc or rtxc, whichever is supplying the transmit clock. 3. both rtxc and sync have 30-pf capacitors to ground connected to them. 4. parameter applies only if the data rate is one-fourth the pclk rate. in all other cases, no phase relationship between rxc and pclk or txc and pclk is required. 5. parameter applies only to fm encoding/decoding. 6. parameter applies only for transmitter and receiver; dpll and baud rate generator timing requirements are identical to chip pclk requirements. 7. the maximum receive or transmit data is 1/4 pclk. 8. external pclk to rxc or txc synchronization requirement eliminated for pclk divide-by-four operation. trxc and rtxc rise and fall times are identical to pclk. reference timing specs tfpc and trpc. tx and rx input clock slew rates should be kept to a maximum of 30 ns. all parameters related to input clk edges should be referenced at the point at which the transition begins or ends, whichever is the worst case. 9. enhanced feature rtxc used as input to internal dpll only. no. parameter symbol parameter description 10 mhz 20 mhz min max min max unit 8.192 mhz min max min max 16.384 mhz industrial only
a m e n d m e n t amd 12 am85c30 1 tdrxc(req) rxc - w / req valid delay 8 12 8 12 tcpc (note 2) 2 tdrxc(w) rxc - to wait inactive delay 8 14 8 14 tcpc (notes 1, 2) 3 tdrxc(sy) rxc - to sync valid delay 4 7 4 7 tcpc (note 2) 4 tdrxc(int) rxc - to int valid delay 10 16 10 16 tcpc (notes 1, 2) 5 tdtxc(req) txc to w / req valid delay 5 8 5 8 tcpc (note 3) 6 tdtxc(w) txc to wait inactive delay 5 11 5 11 tcpc (notes 1, 3) 7a tdtxc(drq) txc to dtr / req valid delay 4 7 4 7 tcpc (note 3) 7b tdtxc(edrq) txc to dtr / req valid delay 5 8 5 8 tcpc (notes 3, 4) 8 tdtxc(int) txc to int valid delay 6 10 6 10 tcpc (notes 1, 3) 9 tdsy(int) sync transition to int valid 2 6 2 6 tcpc delay (note 1) 10 tdext(int) dcd or cts transition to int 2 6 2 6 tcpc valid delay (note 1) switching characteristics over military/industrial operating range (continued)system timing (see figure 20) 1 tdrxc(req) rxc - w / req valid delay 8 12 8 12 tcpc (note 2) 2 tdrxc(w) rxc - to wait inactive delay 8 14 8 14 tcpc (notes 1, 2) 3 tdrxc(sy) rxc - to sync valid delay 4 7 4 7 tcpc (note 2) 4 tdrxc(int) rxc - to int valid delay 10 16 10 16 tcpc (notes 1, 2) 5 tdtxc(req) txc - to w / req valid delay 5 8 5 8 tcpc (note 3) 6 tdtxc(w) txc to wait inactive delay 5 11 5 11 tcpc (notes 1, 3) 7a tdtxc(drq) txc to dtr / req valid delay 4 7 4 7 tcpc (note 3) 7b tdtxc(edrq) txc to dtr / req valid delay 5 8 5 8 tcpc (notes 3, 4) 8 tdtxc(int) txc to int valid delay 6 10 6 10 tcpc (notes 1, 3) 9 tdsy(int) sync transition to int valid 2 6 2 6 tcpc delay (note 1) 10 tdext(int) dcd or cts transition to int 2 6 2 6 tcpc valid delay (note 1) notes : 1. open-drain output, measured with open-drain test load. 2. rxc is rtxc or trxc , whichever is supplying the receive clock. 3. txc is trxc or rtxc , whichever is supplying the transmit clock. 4. parameter applies to enhanced request mode only. no. parameter symbol parameter description 8.192 mhz 10 mhz min max min max unit no. parameter symbol parameter description 16.384 mhz min max unit min max 20 mhz industrial only
a m e n d m e n t amd 13 am85c30 switching characteristics over military/industrial operating range (continued) read and write timing (see figure 21) 1 twpci pclk low width 50 1000 40 1000 26 1000 22 1000 ns 2 twpch pclk high width 50 1000 40 1000 26 1000 22 1000 ns 3 tfpc pclk fall time 15 12 8 5 ns 4 trpc pclk rise time 15 12 8 5 ns 5 tcpc pclk cycle time 122 2000 100 2000 61 2000 50 2000 ns 6 tsa(wr) address to wr setup time 70 50 35 30 ns 7 tha(wr) address to wr - hold time 0000ns 8 tsa(rd) address to rd setup time 70 50 35 30 ns 9 tha(rd) address to rd - hold time 0000ns 10 tsia(pc) i ntack to pclk - setup time 20 20 15 15 ns 11 tsia(wr) intack to wr setup time 145 120 70 65 ns (note 1) 12 thia(wr) intack to wr - hold time 0000ns 13 tsia(rd) intack to rd setup time 145 120 70 65 ns (note 1) 14 thiai(rd) intack to rd - hold time 0000ns 15 thia(pc) intack to pclk - hold time 40 30 15 15 ns 16 tscei(wr) ce low to wr setup time 0000ns 17 thce(wr) ce to wr - hold time 0000ns 18 tsceh(wr) ce high to wr setup time 60 50 30 25 ns 19 tscei(rd) ce low to rd setup time 0000ns (note 1) 20 thce(rd) ce to rd - hold time (note1) 0000ns 21 tsceh(rd) ce high to rd setup time 60 50 30 25 ns (note 1) 22 twrdi rd low width (note 1) 150 125 75 65 ns 23 tdrd(dra) rd to read data active delay 0000ns 24 tdrdr(dr) rd - to read data not valid delay 0000ns 25 tdrdf(dr) rd to read data valid delay 140 125 70 65 ns 26 tdrd(drz) rd - to read data float delay 40 35 20 20 ns (note 2) notes: 1. parameter does not apply to interrupt acknowledge transactions. 2. float delay is defined as the time at which the data bus is released from its drive state with a maximum dc load and minimum ac load. no. parameter symbol parameter description 10 mhz 20 mhz min max min max unit 8.192 mhz min max min max 16.384 mhz industrial only
a m e n d m e n t amd 14 am85c30 unit switching characteristics over military/industrial operating range (continued) interrupt acknowledge timing, reset timing, cycle timing (see figures 22C24) 27 tda(dr) address required valid to read 220 160 100 90 ns data valid delay 28 twwri wr low width 150 125 75 65 ns 29 tdwrf(dw) wr to write data valid 35 35 20 20 ns 30 thdw(wr) write data to wr - hold time 0000ns 31 tdwr(w) wr to wait valid delay (note 2) 170 100 50 50 ns 32 tdrd(w) rd to wait valid delay (note 2) 170 100 50 50 ns 33 tdwrf(req) wr to w / req not valid delay 170 120 70 65 ns 34 tdrdf(req) rd to w / req not valid delay 170 120 70 65 ns 35a tdwrr(req) wr to dtr / req not valid delay 4tcpc 4tcpc 4tcpc 4tcpc ns 35b tdwrr(ereq) wr to dtr / req not valid delay 120 120 70 65 ns 36 tdrdr(req) rd - to dtr / req not valid delay na na na na ns 37 tdpc(int) pclk to int valid delay (note 2) 500 400 175 160 ns 38 tdiai(rd) intack to rd (acknowledge) 150 125 50 45 ns delay (note 3) 39 twrda rd (acknowledge) width 150 125 75 65 ns 40 tdrda(dr) rd (acknowledge) to read 140 120 70 60 ns data valid delay 41 tsiei(rda) iei to rd (acknowledge) setup 95 80 50 45 ns time 42 thiei(rda) iei to rd - (acknowledge) hold 0000ns time 43 tdiei(ieo) iei to ieo delay time 95 80 45 40 ns 44 tdpc(ieo) pclk - to ieo delay 200 175 80 70 ns 45 tdrda(int) rd to int inactive delay (note 2) 450 320 200 180 ns 46 tdrd(wrq) rd - to wr delay for no reset 15 15 10 10 ns 47 tdwrq(rd) wr - to rd delay for no reset 15 15 10 10 ns 48 twres wr and rd coincident low for 150 100 75 65 ns reset 49 trc valid access recovery time 3.5 3.5 3.5 3.5 (note 1) notes: 1 parameter applies only between transactions involving the escc, if wr/rd falling edge is synchronized to pclk falling edge, then trc = 3tcpc. 2. open-drain output, measured with open-drain test load. 3. parameter is system dependent. for any scc in the daisy chain, tdiai(rd) must be greater than the sum of ddpc(ieo) for the highest priority device in the daisy chain, tsiei(rda) for the scc, and tdiei(ieo) for each device separating them in the daisy chain. 4. parameter applies to enhanced request mode only. no. parameter symbol parameter description 10 mhz 20 mhz min max min max 8.192 mhz min max min max 16.384 mhz industrial only tcpc
a m e n d m e n t amd 15 am85c30 am85c30 hardware reset in software in the absence of a hardware logic or a power-on-reset mechanism, the following procedure should be used to ensure that the escc is properly reset. 1. power up 2. read rr0 (dummy read) 3. read rr1 (dummy read) 4. write a c0h to wr9 (hardware reset) 5. read rr0 (should expect binary 01xxx100 = typically 44h) 6. read rr1 (should expect binary 0x000110 = typically 06h) 7. write a value to write register 2 8. read rr2 (should get a value) if rr2 = wr2, in steps 7 and 8, then the escc is prop- erly reset. note: for hardware reset only steps 1 through 4 are needed; steps 5 through 8 are mentioned simply for confirmation. also, this procedure is applicable to only the first time hardware reset. any subsequent chip reset can be achieved by simply writing a c0 to wr9. for further information refer to the technical manual pid # 07513d.

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